JPWO2016195005A1 - アクティブマトリクス基板 - Google Patents
アクティブマトリクス基板 Download PDFInfo
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- JPWO2016195005A1 JPWO2016195005A1 JP2017522239A JP2017522239A JPWO2016195005A1 JP WO2016195005 A1 JPWO2016195005 A1 JP WO2016195005A1 JP 2017522239 A JP2017522239 A JP 2017522239A JP 2017522239 A JP2017522239 A JP 2017522239A JP WO2016195005 A1 JPWO2016195005 A1 JP WO2016195005A1
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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Abstract
Description
以下、図面を参照し、本発明の実施の形態を詳しく説明する。図中同一または相当部分には同一符号を付してその説明は繰り返さない。なお、説明を分かりやすくするために、以下で参照する図面においては、構成が簡略化または模式化して示されたり、一部の構成部材が省略されたりしている。また、各図に示された構成部材間の寸法比は、必ずしも実際の寸法比を示すものではない。
以下では、アクティブマトリクス基板上に光電変換素子を配置したフォトセンサ基板を例に挙げて説明する。フォトセンサ基板は、フォトセンサやX線画像検出装置等に使用され得る。
変換された電荷は、ゲート線Gから供給される信号によりTFT2がオン状態になると、ソース線Sを介して外部へ取り出される。これにより、受光量に応じた電気信号が出力される。このようにして、フォトセンサ基板10は、各センサ部1に照射された光の照射量を電流量に変換し、電気信号として出力する。その結果、各センサ部1の状態に対応する画像が得られる。
図5A〜図5Hは、本実施形態におけるフォトセンサ基板の製造工程の例を示す図である。図5A〜図5Hは、センサ部1が形成される部分の断面を示している。
基板31は、例えばガラス基板、シリコン基板、耐熱性を有するプラスチック基板又は樹脂基板等である。プラスチック基板又は樹脂基板としては、例えば、ポリエチレンテレフタレート(PET)、ポリエチレンナフタレート(PEN)、ポリエーテルサルフォン(PES)、アクリル、ポリイミド等を用いることができる。
基板31上にゲート電極20を形成する。ゲート電極20は、基板31上に導電膜を成膜することによって形成する。導電膜として、アルミニウム(Al)、タングステン(W)、モリブデン(Mo)、タンタル(Ta)、クロム(Cr)、チタン(Ti)、銅(Cu)、等の金属、又はその合金、若しくはその金属窒化物を適宜用いることができる。また、これら複数の層を積層して形成してもよい。
続いて、基板31及びゲート電極20を覆うように、ゲート絶縁膜32を形成する(図5B参照)。ここでは、2層の積層構造でゲート絶縁膜32を形成する。ゲート絶縁膜32は、例えば、酸化珪素(SiOx)、窒化珪素(SiNx)、酸化窒化珪素(SiOxNy)(x>y)、窒化酸化珪素(SiNxOy)(x>y)等を適宜用いることができる。基板31からの不純物等の拡散防止のため、下層側のゲート絶縁膜32としては、窒化珪素(SiNx)、窒化酸化珪素(SiNxOy)(x>y)等を用いて形成し、上層側のゲート絶縁膜32としては、酸化珪素(SiOx)、酸化窒化珪素(SiOxNy)(x>y)等を用いて形成することが望ましい。アルゴンなどの希ガス元素を反応ガスに含ませて絶縁膜中に混入させてもよい。これにより、低い成膜温度でゲートリーク電流の少ない緻密な絶縁膜を形成することができる。
次に、ゲート絶縁膜32上に、半導体層22を形成する(図5B参照)。半導体層22は、例えば、例えばIn−Ga−Zn−O系の半導体(以下、「In−Ga−Zn−O系半導体」と略する。)を含む。ここで、In−Ga−Zn−O系半導体は、In(インジウム)、Ga(ガリウム)、Zn(亜鉛)の三元系酸化物であって、In、GaおよびZnの割合(組成比)は特に限定されず、例えばIn:Ga:Zn=2:2:1、In:Ga:Zn=1:1:1、In:Ga:Zn=1:1:2等を含む。半導体層22は、例えば、InGaO3(ZnO)5を含んでもよい
続いて、ゲート絶縁膜32及び半導体層22の一部の上に導電膜を形成し、レジストマスクを用いたエッチングを含むフォトリソグラフィプロセスによって所定の形状(パターン)に加工し、ソース電極21及びドレイン電極23を形成する(図5C参照)。導電膜として、例えば、アルミニウム(Al)、タングステン(W)、モリブデン(Mo)、タンタル(Ta)、銅(Cu)、クロム(Cr)、チタン(Ti)等の金属又はその合金、若しくはその金属窒化物を適宜用いることができる。また、これら複数の層を積層して形成してもよい。
ソース電極21、半導体層22、及びドレイン電極23を覆うように、第1パッシベーション膜33を成膜する(図5D参照)。第1パッシベーション膜33の厚さは、例えば200〜600nmである。第1パッシベーション膜33は、プラズマCVD法又はスパッタリング法などの薄膜形成法を用い、窒化珪素、酸化珪素、窒化酸化珪素、酸化窒化珪素等の絶縁性材料を用いて形成することができる。なお、第1パッシベーション膜33は、単層に限らず、2層以上とすることができる。また、基板全面に対して熱処理を行ってもよい。
続いて、第1パッシベーション膜33上に、下部電極41を形成するための導電膜を成膜する(図5D参照)。導電膜は、コンタクトホールCH3を介してドレイン電極23と接続されるように形成する。導電膜として、例えば、アルミニウム(Al)、タングステン(W)、モリブデン(Mo)、タンタル(Ta)、銅(Cu)、クロム(Cr)、チタン(Ti)等の金属又はその合金、若しくはその金属窒化物を適宜用いることができる。また、これら複数の層を積層して形成してもよい。
第1パッシベーション膜33及び下部電極41を覆うように、基板31の全面に、n型半導体層、i型半導体層及びp型半導体層をこの順に、例えばCVD法により成膜する。これらの半導体層は、半導体膜42を形成するためのものである。その後、IZOやITO等の透明導電材料を、スパッタリング法によって半導体膜42が形成される領域を含む領域に成膜する。透明導電材料は、上部電極43のための導電体である。その後、フォトリソグラフィプロセス及びドライエッチングによって所定の形状(パターン)に加工することにより、半導体膜42および上部電極43を形成する(図5E参照)。これにより、下部電極41、半導体膜42及び上部電極43が積層されてなるフォトダイオード4が形成される。
続いて、TFT2上、及びフォトダイオード4の側面及び上面の端部を覆うように、第2パッシベーション膜34を形成する(図5F参照)。第2パッシベーション膜34の材料及び形成方法は、第1パッシベーション膜33の材料及び形成方法と同じとすることができる。第2パッシベーション膜34の厚さは、例えば100〜200nmである。
ソース電極21の上部において、レジストマスクを用いたエッチングを含むフォトリソグラフィプロセスによって、第1パッシベーション膜33、第2パッシベーション膜34、及び平坦化膜35にコンタクトホールCH2を形成する。そして、平坦化膜35の上に導電膜を成膜してソース線Sを形成し、フォトダイオード4の上部電極43の上に導電膜を成膜してバイアス線8を形成する(図5H参照)。ソース線Sを構成する導電膜は、コンタクトホールCH2を介してソース電極21と接続されるように形成する。導電膜として、例えばアルミニウム(Al)、モリブデン(Mo)、チタン(Ti)等の金属を用いることができる。
上述した第1の実施形態では、TFT2はボトムゲート型であった。第2の実施形態では、TFT2はトップゲート型である。
図9A〜図9Gは、本実施形態におけるフォトセンサ基板の製造工程の例を示す図である。図9A〜図9Gは、センサ部1が形成される部分の断面を示している。なお、以下の説明において、第1の実施形態と構成材料や膜厚が同じ構成要素については、その説明を省略し、材料や膜厚が異なる部分についてのみ詳しく説明する。
図10は、図1に示すフォトセンサ基板10をX線画像検出装置へ適用した場合の構成例を示す図である。図10は、フォトセンサ基板10の基板に垂直な面における層構成を示している。フォトセンサ基板10のセンサ領域に重なる位置に、シンチレータ層13が設けられる。シンチレータ層13は、例えば、X線を可視光に変換する蛍光体により形成することができる。蛍光体の例として、ヨウ化セシウム(CsI)等が挙げられる。シンチレータ層13は、フォトセンサ基板10の表面に貼り付け又は蒸着等の直接成膜によって形成することができる。シンチレータ層13の上には、シンチレータ層13を覆う保護層14を設けることができる。この構成により、X線画像の平面検出器(FDP:flat panel detector)が実現できる。
10 フォトセンサ基板
2 TFT(トランジスタの一例)
20、20A ゲート電極
21 ソース電極
22 半導体層
23 ドレイン電極
31 基板
34 第2パッシベーション膜
34A パッシベーション膜
35 平坦化膜
41 下部電極
42 半導体膜
43 上部電極
4 フォトダイオード(光電変換素子の一例)
S ソース線
G ゲート線
Claims (6)
- 基板と、
前記基板に配置され、第1方向に延びる複数の第1配線と、
前記基板に配置され、前記第1方向とは異なる第2方向に延びる複数の第2配線と、
前記第1配線と前記第2配線との各交点に対応して配置され、前記第1配線及び前記第2配線と接続されているトランジスタと、
絶縁層と、
を備え、
前記第1配線及び前記第2配線の少なくとも一方は、前記トランジスタの電極と前記絶縁層のコンタクトホールを介して接続されており、前記絶縁層のコンタクトホールを介して接続されている前記トランジスタの電極と比べて、厚い膜厚及び抵抗率の小さい材料の少なくとも一方により形成されている、アクティブマトリクス基板。 - 前記トランジスタは、ゲート電極と、ゲート絶縁膜と、前記ゲート電極と前記ゲート絶縁膜を挟んで対向する位置に設けられている半導体層と、前記半導体層と接続され、前記基板に平行な方向に互いに対向して設けられているドレイン電極及びソース電極とを有し、
前記第1配線は、前記ドレイン電極及び前記ソース電極と同じ層に形成され、前記ゲート絶縁膜のコンタクトホールを介して前記ゲート電極と接続されており、
前記第2配線は、前記ゲート絶縁膜に重ねて配置されている前記絶縁層のコンタクトホールを介して前記トランジスタの前記ドレイン電極又は前記ソース電極に接続されている、請求項1に記載のアクティブマトリクス基板。 - 前記絶縁層は、前記トランジスタを覆うパッシベーション膜を含み、
前記アクティブマトリクス基板は、前記第1配線と前記第2配線との各交点に対応して配置されており、前記パッシベーション膜のコンタクトホールを介して前記トランジスタと接続されている光電変換素子をさらに備える、請求項1又は2に記載のアクティブマトリクス基板。 - 前記絶縁層は、前記トランジスタを覆うパッシベーション膜を含み、
前記アクティブマトリクス基板は、前記第1配線と前記第2配線との各交点に対応して配置されており、前記ゲート絶縁膜のコンタクトホールを介して前記トランジスタと接続されている光電変換素子をさらに備える、請求項2に記載のアクティブマトリクス基板。 - 前記絶縁層は、前記パッシベーション膜の前記光電変換素子が設けられていない部分に設けられている平坦化膜をさらに含み、
前記基板に垂直な方向から見て、前記第1配線と前記第2配線が交差する部分において、前記第1配線と前記第2配線の間に、前記パッシベーション膜及び前記平坦化膜が配置されている、請求項3または4に記載のアクティブマトリクス基板。 - 前記トランジスタのゲート電極は、前記ゲート絶縁膜と前記基板との間に設けられている、請求項2に記載のアクティブマトリクス基板。
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