JPWO2006118019A1 - Image recognition implementation method - Google Patents

Image recognition implementation method Download PDF

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JPWO2006118019A1
JPWO2006118019A1 JP2007514595A JP2007514595A JPWO2006118019A1 JP WO2006118019 A1 JPWO2006118019 A1 JP WO2006118019A1 JP 2007514595 A JP2007514595 A JP 2007514595A JP 2007514595 A JP2007514595 A JP 2007514595A JP WO2006118019 A1 JPWO2006118019 A1 JP WO2006118019A1
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chip
electrode
substrate
alignment mark
image
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JP5065889B2 (en
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寺田　勝美
勝美 寺田
雅史 千田
雅史 千田
幸治 西村
幸治 西村
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Toray Engineering Co Ltd
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Abstract

チップのアライメントマークと基板のアライメントマークを実装前に認識手段で画像認識してチップと基板のアライメントを行い、チップの突起電極と基板の電極を接合する実装方法において、チップのアライメントマークを認識手段で画像認識した後にチップのアライメントマークから所定の位置に形成された突起電極の外観を認識手段で画像認識して突起電極の位置の座標を計算し、突起電極のアライメントマークからの位置ずれ量を補正してチップと基板の接合を行う画像認識実装方法。チップの突起電極の位置がチップの電極の中央に配置されていない場合にあっても、所望の良好な接合を行うことができる。The chip alignment mark and the substrate alignment mark are image-recognized by a recognition unit before mounting, the chip and the substrate are aligned, and the chip alignment mark is recognized in the mounting method in which the chip protruding electrode and the substrate electrode are joined. After recognizing the image, the appearance of the protruding electrode formed at a predetermined position from the chip alignment mark is recognized by the recognition means to calculate the coordinates of the protruding electrode position, and the amount of positional deviation of the protruding electrode from the alignment mark is calculated. An image recognition mounting method that corrects and bonds the chip and the substrate. Even when the position of the protruding electrode of the chip is not arranged at the center of the electrode of the chip, desired good bonding can be performed.

Description

本発明は、半導体チップの回路基板への実装において、チップの突起電極の位置を精度良く検出し突起電極と回路基板の電極の位置ずれを吸収して実装する方法に関する。   The present invention relates to a method for mounting a semiconductor chip on a circuit board by accurately detecting the position of the protruding electrode of the chip and absorbing the positional deviation between the protruding electrode and the electrode of the circuit board.

半導体チップを回路基板に実装する方法として、半導体チップの電極パッド上に形成された突起電極と回路基板の電極を位置合わせして、加圧および加熱して接合する方法が知られている。半導体チップの電極パッド上に形成された突起電極は、一般にスタッドバンプと呼ばれている。このスタッドバンプは、半導体チップの電極パッドにワイヤボンディング法を用いて所定量の金ワイヤを付着させた後、金ワイヤの供給を止めた状態でワイヤボンディングのツールを半導体チップから遠ざけ、金ワイヤを引きちぎって形成させている。また、回路基板はセラミック基板やガラス・エポキシ樹脂基板が用いられ、回路基板上に各種配線と電気的に接続された電極が設けられている。この電極（インナーリード）は、その断面視が回路基板から離れるに従って幅が狭くなる略台形状に形成されている。特許文献１には、半導体チップに形成されたスタッドバンプと回路基板の電極とを対向して配置し、電極の幅をスタッドバンプの幅と同等以下に形成し、スタッドバンプの先端部が電極の幅と同程度の幅になるまで熱圧着してスタッドバンプと電極の接合を行い、接合後に接合部を樹脂で封止する方法が開示されている。   As a method for mounting a semiconductor chip on a circuit board, a method is known in which a protruding electrode formed on an electrode pad of a semiconductor chip and an electrode of a circuit board are aligned and bonded by pressing and heating. The protruding electrode formed on the electrode pad of the semiconductor chip is generally called a stud bump. This stud bump is made by attaching a predetermined amount of gold wire to the electrode pad of the semiconductor chip by using the wire bonding method, and then keeping the wire bonding tool away from the semiconductor chip while the supply of the gold wire is stopped. It is formed by tearing. In addition, a ceramic substrate or a glass / epoxy resin substrate is used as the circuit board, and electrodes electrically connected to various wirings are provided on the circuit board. The electrode (inner lead) is formed in a substantially trapezoidal shape whose width is narrowed as the sectional view is separated from the circuit board. In Patent Document 1, a stud bump formed on a semiconductor chip and an electrode of a circuit board are arranged to face each other, the width of the electrode is formed to be equal to or less than the width of the stud bump, and the tip of the stud bump is the electrode. There is disclosed a method in which a stud bump and an electrode are bonded by thermocompression bonding until the width is approximately equal to the width, and the bonded portion is sealed with a resin after bonding.

近年の電子部品の高密度実装化は、半導体チップの端子のファインピッチ化やチップ部品が実装される回路基板のパターンの微細化によって対応されている。そのため、ファインピッチ化が進み、１０μｍから３０μｍの電極の幅の回路基板への半導体チップの実装が求められている。このようなファインピッチの回路基板の電極に接合する半導体チップのスタッドバンプは、バンプの径が１５μｍから３５μｍ程度であり、例えば図２に示すように、電極２の前後左右等の片側に電極２の中心より位置ずれしていることがごくまれにある。このため、例えば図７に示すように、チップ１と回路基板４を接合する際、チップ１のスタッドバンプ３が回路基板４の電極５の中央に配置されず、片側に寄ってしまい、実装時にスタッドバンプ３が矢印で示すように横滑りしてしまい、実装不良を引き起こすことがあった。   In recent years, high-density mounting of electronic components is supported by finer pitches of semiconductor chip terminals and finer circuit board patterns on which chip components are mounted. For this reason, the fine pitch has been advanced, and there is a demand for mounting a semiconductor chip on a circuit board having an electrode width of 10 μm to 30 μm. A stud bump of a semiconductor chip to be bonded to an electrode of such a fine pitch circuit board has a bump diameter of about 15 μm to 35 μm. For example, as shown in FIG. Very rarely, it is misaligned from the center. For this reason, for example, as shown in FIG. 7, when the chip 1 and the circuit board 4 are joined, the stud bump 3 of the chip 1 is not arranged at the center of the electrode 5 of the circuit board 4, but is shifted to one side, The stud bump 3 slips as indicated by an arrow, which may cause mounting failure.

また、回路基板４の伸びなどにより、電極５の位置が回路基板４のアライメントマークから位置ずれし、チップ１と回路基板４のアライメントマーク同士を合わせて行う実装では実装不良を引き起こすことがあるという問題もあった。
特開２００３−３３２３７４号公報 Further, the position of the electrode 5 is displaced from the alignment mark of the circuit board 4 due to the elongation of the circuit board 4 and the like, and the mounting performed by aligning the alignment marks of the chip 1 and the circuit board 4 may cause a mounting failure. There was also a problem.
JP 2003-332374 A

そこで本発明の課題は、上記問題点に鑑み、チップのスタッドバンプの位置がチップの電極の中心に配置されていなくても、良好な接合をすることができる電子部品の実装方法を提供することにある。   Therefore, in view of the above problems, an object of the present invention is to provide an electronic component mounting method that can perform good bonding even if the position of the stud bump of the chip is not arranged at the center of the electrode of the chip. It is in.

また本発明は、チップと回路基板のアライメントマーク同士を合わせて行う実装における実装不良を回避することも課題とする。   Another object of the present invention is to avoid mounting defects in the mounting performed by aligning the alignment marks of the chip and the circuit board.

上記課題を解決するために、本発明に係る画像認識実装方法は、チップのアライメントマークと基板のアライメントマークを実装前に認識手段で画像認識してチップと基板のアライメントを行い、チップの突起電極と基板の電極を接合する実装方法において、チップのアライメントマークを認識手段で画像認識した後にチップのアライメントマークから所定の位置に形成された突起電極の外観を認識手段で画像認識して突起電極の位置の座標を計算し、突起電極のアライメントマークからの位置ずれ量を補正してチップと基板の接合を行うことを特徴とする方法からなる。   In order to solve the above-described problems, an image recognition mounting method according to the present invention performs image recognition on a chip alignment mark and a substrate alignment mark by a recognition means before mounting to align the chip and the substrate, and a protruding electrode on the chip. In the mounting method of joining the electrodes of the substrate and the substrate, after the image of the alignment mark of the chip is recognized by the recognition means, the appearance of the protruding electrode formed at a predetermined position from the alignment mark of the chip is image-recognized by the recognition means. The method is characterized in that the position coordinates are calculated, the amount of positional deviation of the protruding electrode from the alignment mark is corrected, and the chip and the substrate are joined.

この画像認識実装方法においては、基板のアライメントマークを実装前に認識手段で画像認識するに際し、基板のアライメントマークを認識手段で画像認識した後に基板のアライメントマークから所定の位置に形成された電極の外観を認識手段で画像認識して電極の位置の座標を計算し、基板の電極のアライメントマークからの位置ずれ量を補正してチップと基板の接合を行うようにすることができる。   In this image recognition mounting method, when the substrate alignment mark is image-recognized by the recognition means before mounting, after the image recognition of the substrate alignment mark by the recognition means, the electrode formed at a predetermined position from the substrate alignment mark. It is possible to perform the image recognition by the recognition means to calculate the coordinates of the position of the electrode, correct the positional deviation amount of the electrode of the substrate from the alignment mark, and bond the chip and the substrate.

また、上記画像認識実装方法においては、チップを搬送するチップ搬送手段のチップ保持板を透明部材で構成し、チップを搬送するに際し、チップに形成された突起電極をチップ搬送手段の下方に配置された認識手段で画像認識し、チップの突起電極の位置を認識するようにすることもできる。つまり、チップの搬送中に突起電極を画像認識できるようにした構成である。   Further, in the image recognition mounting method, the chip holding plate of the chip conveying means for conveying the chip is made of a transparent member, and when the chip is conveyed, the protruding electrode formed on the chip is arranged below the chip conveying means. It is also possible to recognize the image by the recognition means and recognize the position of the protruding electrode of the chip. In other words, the protruding electrode can be image-recognized during the conveyance of the chip.

さらに、上記画像認識実装方法においては、予め突起電極の平均的な画像パターンを登録しておき、チップに形成された突起電極を認識手段で画像認識し、前記平均的な画像パターンと認識手段で画像認識した画像パターンの比較を行い、チップの突起電極の位置を認識するようにすることもできる。   Further, in the image recognition mounting method, an average image pattern of the protruding electrodes is registered in advance, and the protruding electrodes formed on the chip are image-recognized by a recognition unit, and the average image pattern and the recognition unit are used. It is also possible to compare image patterns that have been image-recognized to recognize the positions of the protruding electrodes of the chip.

本発明に係る画像認識実装方法によれば、チップと基板のアライメントマークを基準にして位置合わせし実装を行うのではなく、チップの突起電極を画像認識して突起電極の位置を正確に把握し、その突起電極と基板をアライメントするので、突起電極がチップの電極の中心部から外れた位置に形成されていたとしても、基板に対して目標とする位置関係をもって高精度にチップを実装することができる。   According to the image recognition mounting method according to the present invention, rather than performing alignment and mounting with reference to the alignment mark of the chip and the substrate, image recognition is performed on the protruding electrode of the chip to accurately grasp the position of the protruding electrode. Because the protruding electrode and the substrate are aligned, even if the protruding electrode is formed at a position away from the center of the chip electrode, the chip can be mounted with a target positional relationship with high accuracy with respect to the substrate. Can do.

また、基板の電極位置を画像認識してアライメントするようにすれば、基板の伸びなどにより基板の電極がアライメントマークから位置ずれしていたとしても、所定の良好な接合を達成することが可能になる。   Also, if the electrode position of the substrate is recognized and aligned, even if the substrate electrode is displaced from the alignment mark due to the elongation of the substrate, it is possible to achieve a predetermined good bonding. Become.

また、チップ搬送手段のチップ保持板を透明部材で構成してチップの搬送中に突起電極を画像認識できるようにすれば、接合工程全体としてのタクトタイムの短縮をはかることが可能になる。   Further, if the chip holding plate of the chip transfer means is made of a transparent member so that the protruding electrodes can be recognized during the transfer of the chip, the tact time as a whole bonding process can be shortened.

さらに、予め突起電極の平均的な画像パターンを登録しておき、それと画像認識した画像パターンとの比較を行うようにすれば、チップに突起電極を形成する時に突起電極の一部が欠如していたとしても、予め登録された突起電極の画像パターンとの差が少なければ、実装することが可能となるので、突起電極の作成の精度がそれほど要求されなくなり、歩留まりが上がって、実装効率が上がる。   Furthermore, if an average image pattern of bump electrodes is registered in advance and compared with an image pattern that has been recognized, a portion of the bump electrodes is missing when the bump electrodes are formed on the chip. Even if the difference from the image pattern of the projecting electrode registered in advance is small, mounting is possible, so that the accuracy of creating the projecting electrode is not so required, yield is increased, and mounting efficiency is increased. .

本発明の一実施形態に係る実装方法を実施するための実装装置の要部正面図である。It is a principal part front view of the mounting apparatus for enforcing the mounting method which concerns on one Embodiment of this invention. チップのスタッドバンプ形成面を説明する図である。It is a figure explaining the stud bump formation surface of a chip. 画像認識処理時に使用する登録データと検出データを説明する図である。It is a figure explaining the registration data and detection data which are used at the time of image recognition processing. 基板の電極とアライメントマークの位置関係を説明する図である。It is a figure explaining the positional relationship of the electrode of a board | substrate, and an alignment mark. 本発明の一実施形態に係る画像認識実装方法のフロチャートである。It is a flowchart of the image recognition mounting method which concerns on one Embodiment of this invention. チップ搬送手段に保持されたチップを下方から画像認識する方法を説明する斜視図である。It is a perspective view explaining the method of image-recognizing the chip | tip hold | maintained at the chip | tip conveying means from the downward direction. 従来の実装方法における不具合を示すチップと基板の断面図である。It is sectional drawing of the chip | tip and a board | substrate which show the malfunction in the conventional mounting method.

符号の説明Explanation of symbols

１ チップ
２ 電極
３ スタッドバンプ（突起電極）
４ 基板
５ 電極
６ ボンディングヘッド
７ ボンディングステージ
８ ２視野カメラ
９ アライメントマーク
１０ 電極中心
１１ スタッドバンプ中心
１２ 中心位置
１３ アライメントマーク
１４ 中心位置
１５ チップ搬送手段
１６ ＣＣＤカメラ
１７ 透明部材
１８ 固定レール1 Chip 2 Electrode 3 Stud bump (projection electrode)
4 Substrate 5 Electrode 6 Bonding Head 7 Bonding Stage 8 2 Field of View Camera 9 Alignment Mark 10 Electrode Center 11 Stud Bump Center 12 Center Position 13 Alignment Mark 14 Center Position 15 Chip Conveying Device 16 CCD Camera 17 Transparent Member 18 Fixed Rail

以下に、本発明の一実施形態について、図面を参照して説明する。
図１は、本発明の一実施形態に係る画像認識実装方法を実施するためのフリップチップ実装装置の要部正面図である。この実装装置の接合部は、チップ１を吸着保持するボンディングヘッド６と、基板４を吸着保持するボンディングステージ７と、認識手段である２視野カメラ８から構成されている。ボンディングヘッド６は昇降可能になっており、ボンディングステージ７はＸ、Ｙ、θ方向に移動可能になっている。２視野カメラ８は、ボンディングヘッド６とボンディングステージ７の間に挿入できるよう、進退可能に構成されている。実装装置の接合部へのチップ１の搬送は、図示していないチップ吸着反転ツールを用いて行われるようになっている。基板４の搬送は、図示していない基板搬送ツールで行われるようになっている。An embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a front view of an essential part of a flip chip mounting apparatus for carrying out an image recognition mounting method according to an embodiment of the present invention. The bonding portion of this mounting apparatus is composed of a bonding head 6 that holds the chip 1 by suction, a bonding stage 7 that holds the substrate 4 by suction, and a two-field camera 8 that is a recognition means. The bonding head 6 can move up and down, and the bonding stage 7 can move in the X, Y, and θ directions. The two-field camera 8 is configured to be able to advance and retract so that it can be inserted between the bonding head 6 and the bonding stage 7. The conveyance of the chip 1 to the joint portion of the mounting apparatus is performed using a chip adsorption / reversal tool (not shown). The substrate 4 is transferred by a substrate transfer tool (not shown).

図２に、チップ１の実装面である突起電極としてのスタッドバンプ３の形成面を示す。スタッドバンプ３形成面には、チップ１のアライメントマーク９と複数の電極２が形成されている。各電極２の上に、突起電極としてのスタッドバンプ３が形成されている。スタッドバンプ３は、前工程でワイヤボンディング法で金ワイヤを電極２に付着させる際、位置精度良く付着させることが困難なため、図示例では、電極２の電極中心１０より上下左右にずれた位置に形成されている。   FIG. 2 shows a formation surface of the stud bump 3 as a protruding electrode which is a mounting surface of the chip 1. An alignment mark 9 of the chip 1 and a plurality of electrodes 2 are formed on the surface on which the stud bump 3 is formed. A stud bump 3 as a protruding electrode is formed on each electrode 2. In the illustrated example, the stud bumps 3 are shifted vertically and horizontally from the electrode center 10 of the electrode 2 because it is difficult to attach the gold wire to the electrode 2 with a wire bonding method in the previous process. Is formed.

次に、本発明に係る画像認識実装方法について、図５のフロチャートを使用して説明する。まず、前工程でチップ１の電極２にスタッドバンプ３が形成されたチップ１が吸着反転ツールを用いて、ボンディングヘッド６に吸着保持される。また、電極５を有した基板４が基板搬送ツールでボンディングステージ７に搬送され吸着保持される（ステップＳ１）。   Next, an image recognition mounting method according to the present invention will be described using the flowchart of FIG. First, the chip 1 in which the stud bump 3 is formed on the electrode 2 of the chip 1 in the previous process is sucked and held by the bonding head 6 using a suction reversal tool. Further, the substrate 4 having the electrodes 5 is transported to the bonding stage 7 by the substrate transport tool and held by suction (step S1).

次に、２視野カメラ８がチップ１と基板４の間に進入する（ステップＳ２）。２視野カメラ８の進入が完了した位置は、チップ１および基板４のアライメントマークが２視野カメラ８の視野範囲に入る位置となる。   Next, the two-field camera 8 enters between the chip 1 and the substrate 4 (step S2). The position where the entry of the two-field camera 8 is completed is a position where the alignment marks of the chip 1 and the substrate 4 fall within the field-of-view range of the two-field camera 8.

次に、２視野カメラ８がチップ１の画像認識を行い、得られた視野範囲の画像データの中から、アライメントマーク９のサーチを行う（ステップＳ３）。この時のサーチ範囲を第１のサーチ範囲Ａ１とする。図２にこの第１のサーチ範囲Ａ１を点線で示す。第１のサーチ範囲Ａ１には２視野カメラ８の視野範囲の全ての画像が含まれるので、複数の電極２およびスタッドバンプ３が存在している。アライメントマーク９と電極２およびスタッドバンプ３の外観は異なるため、アライメントマーク９の予め設定している画像データとの比較（粗サーチ）を第１のサーチ範囲Ａ１で行う。アライメントマーク９のサーチが完了すると、アライメントマーク９から予め設定されている距離だけ離れた第２のサーチ範囲Ａ２をサーチ範囲として、スタッドバンプ３のサーチを行う。図２に第２のサーチ範囲Ａ２を示す。２視野カメラ８はアライメントマーク９を起点として点線で示した第２のサーチ範囲Ａ２内をサーチ（詳細サーチ）する。第２のサーチ範囲Ａ２にスタッドバンプ３が検出されない場合、２視野カメラ８の位置を所定量だけ移動し視野範囲を変更して、再度、第２のサーチ範囲Ａ２を再設定してサーチ動作を行う。   Next, the two-field camera 8 recognizes the image of the chip 1 and searches for the alignment mark 9 from the image data in the obtained field range (step S3). The search range at this time is defined as a first search range A1. FIG. 2 shows the first search range A1 with a dotted line. Since the first search range A1 includes all the images in the field of view of the two-field camera 8, a plurality of electrodes 2 and stud bumps 3 exist. Since the appearance of the alignment mark 9, the electrode 2 and the stud bump 3 is different, a comparison (coarse search) with the image data set in advance of the alignment mark 9 is performed in the first search range A1. When the search for the alignment mark 9 is completed, the stud bump 3 is searched using the second search range A2 separated from the alignment mark 9 by a preset distance as a search range. FIG. 2 shows the second search range A2. The two-field camera 8 searches (detailed search) in the second search range A2 indicated by the dotted line with the alignment mark 9 as a starting point. If the stud bump 3 is not detected in the second search range A2, the position of the two-field camera 8 is moved by a predetermined amount, the field-of-view range is changed, and the second search range A2 is set again to perform the search operation. Do.

次に、サーチ動作の結果、図３に示すような予め設定されている登録スタッドバンプの画像データＲＩＤ（図３（Ａ））に近い画像ＤＩＤ（図３（Ｂ））が検出されると、画像データ同士の比較が図３（Ｃ）に示すように行われる。ここで、図３（Ａ）におけるＢＰは登録スタッドバンプの中心を示している。登録スタッドバンプの画像ＲＩＤの輪郭を表す円を、検出したスタッドバンプ３の画像ＤＩＤに重ね合わせ、図３（Ｃ）に示すように両画像の差分の面積ΔＡを求める（ステップＳ４）。   Next, as a result of the search operation, when an image DID (FIG. 3 (B)) close to the preset registered stud bump image data RID (FIG. 3 (A)) as shown in FIG. 3 is detected, Comparison between the image data is performed as shown in FIG. Here, BP in FIG. 3A indicates the center of the registered stud bump. A circle representing the contour of the image RID of the registered stud bump is superimposed on the detected image DID of the stud bump 3, and an area ΔA of the difference between the two images is obtained as shown in FIG. 3C (step S4).

次に、予め設定してある差分の面積の許容値とステップＳ４で計算した差分の面積を比較する（ステップＳ５）。面積の比率が許容範囲外の場合、スタッドバンプ形成不良として不良品対応の処理を行う（ステップＳ２４）。   Next, the preset difference area allowance is compared with the difference area calculated in step S4 (step S5). If the area ratio is out of the allowable range, the defective bump formation failure is handled as a defective product (step S24).

次に、ステップＳ５で面積の比率が許容範囲以内の場合、検出したスタッドバンプ３の画像データから中心位置１２（図２に図示）を計算する。そして、中心位置１２とアライメントマーク９との位置関係を計算して図２に示すｘ１，ｙ１のデータを取得する（ステップＳ６）。   Next, when the area ratio is within the allowable range in step S5, the center position 12 (shown in FIG. 2) is calculated from the detected image data of the stud bump 3. Then, the positional relationship between the center position 12 and the alignment mark 9 is calculated to obtain the data of x1 and y1 shown in FIG. 2 (step S6).

次に、２視野カメラ８の位置を所定量だけ移動し視野範囲を変更して、得られた視野範囲の画像データの中から、ステップＳ３とは別のアライメントマーク９のサーチを行う（ステップＳ７）。ステップＳ３からステップＳ６までの動作と同様に、別のスタッドバンプ３’についてサーチを行い、スタッドバンプ３’の中心座標ｘ１’，ｙ１’のデータを取得する（ステップＳ７〜Ｓ１０）。   Next, the position of the two-field camera 8 is moved by a predetermined amount to change the field-of-view range, and a search for an alignment mark 9 different from step S3 is performed from the image data of the obtained field-of-view range (step S7). ). Similar to the operation from step S3 to step S6, a search is performed for another stud bump 3 ', and data on the center coordinates x1' and y1 'of the stud bump 3' is obtained (steps S7 to S10).

次に、スタッドバンプ３とスタッドバンプ３’を結ぶ直線の傾きｋ１と直線の中点の座標ｘ３，ｙ３を計算する（ステップＳ１１）。傾きｋ１と座標ｘ３，ｙ３はチップのボンディング基準位置をして用いる。   Next, the straight line k1 connecting the stud bump 3 and the stud bump 3 'and the coordinates x3 and y3 of the midpoint of the straight line are calculated (step S11). The inclination k1 and the coordinates x3 and y3 are used as the bonding reference position of the chip.

次に、２視野カメラ８が基板４のアライメントマーク１３（図４に図示）を画像認識する（基板のアライメントマークの粗サーチ）。そして、アライメントマーク１３から予め設定してある範囲で、基板４の電極５の画像サーチ動作を行う（電極の詳細サーチ）（ステップＳ１２）。   Next, the two-field camera 8 recognizes an image of the alignment mark 13 (illustrated in FIG. 4) on the substrate 4 (rough search for the alignment mark on the substrate). Then, an image search operation of the electrode 5 of the substrate 4 is performed within a preset range from the alignment mark 13 (detailed search for electrodes) (step S12).

次に、サーチ動作の結果、スタッドバンプ３における場合と同様に、登録電極の画像データに近い画像が検出されると、画像データ同士の比較が行われる。登録電極の画像の輪郭で表される四角形を、検出した電極５の画像に重ね合わせて差分の面積を求める（ステップＳ１３）。   Next, as a result of the search operation, when an image close to the image data of the registered electrode is detected as in the case of the stud bump 3, the image data are compared with each other. A square represented by the contour of the registered electrode image is superimposed on the detected image of the electrode 5 to obtain the area of the difference (step S13).

次に、予め設定してある差分の面積の許容値とステップＳ８で計算した差分の面積を比較する（ステップＳ１４）。面積の比率が許容範囲外の場合、電極形成不良として不良品対応の処理を行う（ステップＳ２６）。   Next, the preset difference area allowance is compared with the difference area calculated in step S8 (step S14). If the area ratio is out of the allowable range, processing for defective products is performed as defective electrode formation (step S26).

次に、ステップＳ９で許容範囲以内の場合、検出した電極５の画像データから中心位置１４（図４に図示）を計算する。そして、中心位置１４とアライメントマーク１３との位置関係を計算してｘ２，ｙ２のデータを取得する（ステップＳ１５）。   Next, when it is within the allowable range in step S9, the center position 14 (shown in FIG. 4) is calculated from the detected image data of the electrode 5. Then, the positional relationship between the center position 14 and the alignment mark 13 is calculated to obtain x2 and y2 data (step S15).

次に、２視野カメラ８の位置を所定量だけ移動し視野範囲を変更して、得られた視野範囲の画像データの中から、ステップＳ１２とは別のアライメントマーク１３のサーチを行う（ステップＳ１６）。ステップＳ１２からステップＳ１５までの動作と同様に、別の電極５’についてサーチを行い、電極５’の中心座標ｘ２’，ｙ２’のデータを取得する（ステップＳ１６〜Ｓ１９）。ステップＳ１８において、面積の比率が許容範囲外の場合、電極形成不良として不良品対応の処理を行う（ステップＳ２７）。   Next, the position of the two-field camera 8 is moved by a predetermined amount to change the field-of-view range, and a search for an alignment mark 13 different from step S12 is performed from the image data of the obtained field-of-view range (step S16). ). Similar to the operation from step S12 to step S15, a search is performed for another electrode 5 ', and data on the center coordinates x2' and y2 'of the electrode 5' is obtained (steps S16 to S19). In step S18, if the area ratio is out of the allowable range, an electrode formation failure is handled as a defective product (step S27).

次に、電極５と電極５’を結ぶ直線の傾きｋ２と直線の中点の座標ｘ４，ｙ４を計算する（ステップＳ２０）。傾きｋ２と座標ｘ４，ｙ４は基板のボンディング基準位置をして用いる。   Next, the inclination k2 of the straight line connecting the electrode 5 and the electrode 5 'and the coordinates x4 and y4 of the midpoint of the straight line are calculated (step S20). The inclination k2 and the coordinates x4 and y4 are used as the bonding reference position of the substrate.

次に、チップの傾きｋ１および座標ｘ３，ｙ３と、基板の傾きｋ２および座標ｘ４，ｙ４に基づいて、ボンディングステージ７をＸ、Ｙ、θ方向に動作させアライメントする（ステップＳ２１）。   Next, based on the chip tilt k1 and coordinates x3, y3 and the substrate tilt k2 and coordinates x4, y4, the bonding stage 7 is moved in the X, Y, and θ directions for alignment (step S21).

次に、アライメントが完了すると、ボンディングヘッド６が下降し加圧および加熱が所定時間行われ、チップ１のスタッドバンプ３と基板４の電極５が接合される（ステップＳ２２）。   Next, when the alignment is completed, the bonding head 6 is lowered, pressure and heating are performed for a predetermined time, and the stud bump 3 of the chip 1 and the electrode 5 of the substrate 4 are joined (step S22).

次に、ボンディングヘッド６が上昇されて接合が完了する（ステップＳ２３）。   Next, the bonding head 6 is raised to complete the bonding (step S23).

このように、チップ１のアライメントマーク９と基板のアライメントマーク１３の代わりに、スタッドバンプ３および電極５の位置データに基づいてアライメントが行われチップ１と基板４の接合が行われるので、スタッドバンプ３の位置がチップ１の電極２の中心に形成されていなくても、良好な接合が達成される。また、基板４のアライメントマーク１３と電極５の位置関係が基板の膨張または収縮の影響を受けたとしても、高精度の良好な接合が可能になる。また、スタッドバンプ３の形状が前工程で精度良く形成されていなくても、所定の許容範囲以内の形状ならば、スタッドバンプ３として認識できるので、スタッドバンプ３の良否判定の歩留まりが上がり、生産性が向上する。   Thus, instead of the alignment mark 9 of the chip 1 and the alignment mark 13 of the substrate, the alignment is performed based on the position data of the stud bump 3 and the electrode 5 and the chip 1 and the substrate 4 are joined. Even if the position 3 is not formed at the center of the electrode 2 of the chip 1, good bonding is achieved. Further, even if the positional relationship between the alignment mark 13 of the substrate 4 and the electrode 5 is influenced by the expansion or contraction of the substrate, it is possible to achieve good bonding with high accuracy. Even if the shape of the stud bump 3 is not accurately formed in the previous process, it can be recognized as the stud bump 3 if the shape is within a predetermined allowable range. Improves.

なお、本発明は上述した実施の形態に限らず、次のように変形して実施することもできる。まず、上記実施の形態のステップＳ７以降において、基板４の電極５の画像を検出し電極５の位置データｘ２、ｙ２を求めているが、位置データｘ２、ｙ２の代わりに基板４のアライメントマーク１３の位置データを使用してチップ１と基板４のアライメントを行ってもよい。特に、熱による変形の少ない基板４とチップ１との接合の場合には、電極５の位置データでアライメントする必要がなく、その分タクトタイムを短縮できる。   Note that the present invention is not limited to the above-described embodiment, and can be modified as follows. First, in step S7 and subsequent steps of the above embodiment, the image of the electrode 5 on the substrate 4 is detected to obtain the position data x2 and y2 of the electrode 5, but the alignment mark 13 on the substrate 4 is used instead of the position data x2 and y2. The position data may be used to align the chip 1 and the substrate 4. In particular, in the case of joining the substrate 4 and the chip 1 with little deformation due to heat, it is not necessary to perform alignment with the position data of the electrodes 5, and the tact time can be shortened accordingly.

また、上述の実施の形態では、突起電極はスタッドバンプ３（金やアルミのワイヤーで形成されたバンプ）としているが、半田バンプやメッキバンプであってもよい。   In the above-described embodiment, the protruding electrode is the stud bump 3 (a bump formed of gold or aluminum wire), but may be a solder bump or a plated bump.

なお、スタッドバンプ３、３’の画像認識において、図３（Ｄ）に示すように、照明の反射などのより画像中央部に空きが生じた画像データＤＨＤとなることがある。このような場合においても、スタッドバンプ３もしくは３’の外形を基準にパターンマッチングの処理を行って判定することができる。   In the image recognition of the stud bumps 3 and 3 ′, as shown in FIG. 3D, there may be image data DHD in which a space is generated in the center of the image due to illumination reflection or the like. Even in such a case, determination can be made by performing pattern matching processing based on the outer shape of the stud bump 3 or 3 '.

また、本発明の実施の形態では、ボンディングヘッド６に吸着保持されたチップ１を、２視野カメラ８で画像認識したが、例えば図６に示すように、予め、透過型のチップ搬送手段１５を用いてチップ供給源からボンディングヘッド６にチップ１を搬送する間に、認識手段としてのＣＣＤカメラ１６を用いて画像認識することもできる。   Further, in the embodiment of the present invention, the image of the chip 1 attracted and held by the bonding head 6 is recognized by the two-view camera 8, but for example, as shown in FIG. It is also possible to recognize an image using the CCD camera 16 as a recognition means while the chip 1 is being conveyed from the chip supply source to the bonding head 6.

図６に示すチップ搬送手段１５は、チップ供給源からボンディングヘッド６の下部まで延びる固定レール１８上を移動可能になっており、チップ１をフェイスダウン状態（チップ１のバンプ面が下向き）で搬送することができる。チップ１の吸着保持面は透明部材１７（例えば、ガラスなど）で構成されている。ボンディング作業中に、待機位置に停止したチップ搬送手段１５上のチップ１をＣＣＤカメラ１６で画像認識する。   The chip conveying means 15 shown in FIG. 6 is movable on a fixed rail 18 extending from the chip supply source to the lower part of the bonding head 6, and conveys the chip 1 in a face-down state (the bump surface of the chip 1 faces down). can do. The suction holding surface of the chip 1 is composed of a transparent member 17 (for example, glass). During the bonding operation, the CCD camera 16 recognizes an image of the chip 1 on the chip conveying means 15 stopped at the standby position.

このような構成にすることにより、ボンディング作業時に行われる、チップ１のスタッドバンプ３を画像認識する粗サーチ、詳細サーチを、予め待機位置で行うことができ、タクトタイムを短縮できる。   With such a configuration, a rough search and a detailed search for recognizing the image of the stud bump 3 of the chip 1 performed during the bonding operation can be performed in advance at the standby position, and the tact time can be shortened.

さらに、この上述の実施の形態のフローチャートではチップ１のスタッドバンプ３，３’を２点認識した後に基板４側の電極５，５’を２点認識しているが、２視野カメラ８でスタッドバンプ３，３’と電極５，５’を同時に認識する方式であってもよい。こうすることにより、カメラ移動が２回で済むのでタクトタイムが短くなる。また、スタッドバンプ３，３’と電極５，５’を２視野カメラ８で同時認識することによりカメラ軸の停止精度の影響を受けないので精度の良い実装ができる。   Furthermore, in the flowchart of the above-described embodiment, two points of the electrodes 5 and 5 ′ on the substrate 4 side are recognized after the two stud bumps 3 and 3 ′ of the chip 1 are recognized. A method of simultaneously recognizing the bumps 3 and 3 ′ and the electrodes 5 and 5 ′ may be used. By doing so, the tact time is shortened because the camera needs to be moved only twice. Further, by simultaneously recognizing the stud bumps 3 and 3 'and the electrodes 5 and 5' by the two-field camera 8, it is not affected by the stop accuracy of the camera axis, so that it can be mounted with high accuracy.

さらに、以上の説明は、突起電極としてのスタッドバンプを有するチップの基板への実装について行ったが、本発明は、突起電極が形成された他の電子部品の基板への実装にも展開できる。したがって、本発明においては、突起電極が形成されたチップとは、このような他の電子部品まで含む概念であると解されるべきである。   Furthermore, although the above description was made about mounting a chip having a stud bump as a protruding electrode on a substrate, the present invention can also be applied to mounting another electronic component on which a protruding electrode is formed on a substrate. Therefore, in the present invention, the chip on which the protruding electrode is formed should be understood as a concept including such other electronic components.

本発明に係る画像認識実装方法では、装置を簡素化できるとともに工程を大幅に短縮できるので、本発明は、チップの基板への接合が要求されるあらゆる分野に適用することができる。   In the image recognition mounting method according to the present invention, the apparatus can be simplified and the process can be greatly shortened. Therefore, the present invention can be applied to all fields where bonding of a chip to a substrate is required.

Claims (4)

チップのアライメントマークと基板のアライメントマークを実装前に認識手段で画像認識してチップと基板のアライメントを行い、チップの突起電極と基板の電極を接合する実装方法において、チップのアライメントマークを認識手段で画像認識した後にチップのアライメントマークから所定の位置に形成された突起電極の外観を認識手段で画像認識して突起電極の位置の座標を計算し、突起電極のアライメントマークからの位置ずれ量を補正してチップと基板の接合を行うことを特徴とする画像認識実装方法。   The chip alignment mark and the substrate alignment mark are image-recognized by a recognition unit before mounting, the chip and the substrate are aligned, and the chip alignment mark is recognized in the mounting method in which the chip protruding electrode and the substrate electrode are joined. After recognizing the image, the appearance of the protruding electrode formed at a predetermined position from the chip alignment mark is recognized by the recognition means to calculate the coordinates of the protruding electrode position, and the amount of positional deviation of the protruding electrode from the alignment mark is calculated. An image recognition mounting method comprising correcting and bonding a chip and a substrate. 基板のアライメントマークを実装前に認識手段で画像認識するに際し、基板のアライメントマークを認識手段で画像認識した後に基板のアライメントマークから所定の位置に形成された電極の外観を認識手段で画像認識して電極の位置の座標を計算し、基板の電極のアライメントマークからの位置ずれ量を補正してチップと基板の接合を行うことを特徴とする、請求項１に記載の画像認識実装方法。   When recognizing the substrate alignment mark by the recognition unit before mounting, the recognition unit recognizes the appearance of the electrode formed at a predetermined position from the substrate alignment mark after the substrate alignment mark is recognized by the recognition unit. The image recognition mounting method according to claim 1, wherein the coordinates of the position of the electrode are calculated, the amount of positional deviation from the alignment mark of the electrode of the substrate is corrected, and the chip and the substrate are joined. チップを搬送するチップ搬送手段のチップ保持板を透明部材で構成し、チップを搬送するに際し、チップに形成された突起電極をチップ搬送手段の下方に配置された認識手段で画像認識し、チップの突起電極の位置を認識することを特徴とする、請求項１に記載の画像認識実装方法。   The chip holding plate of the chip transport means for transporting the chip is made of a transparent member, and when the chip is transported, the protruding electrodes formed on the chip are image-recognized by the recognition means disposed below the chip transport means, The image recognition mounting method according to claim 1, wherein the position of the protruding electrode is recognized. 予め突起電極の平均的な画像パターンを登録しておき、チップに形成された突起電極を認識手段で画像認識し、前記平均的な画像パターンと認識手段で画像認識した画像パターンの比較を行い、チップの突起電極の位置を認識することを特徴とする、請求項１〜３のいずれかに記載の画像認識実装方法。   The average image pattern of the bump electrode is registered in advance, the bump electrode formed on the chip is image-recognized by the recognition means, and the average image pattern is compared with the image pattern recognized by the recognition means, The image recognition mounting method according to claim 1, wherein the position of the protruding electrode of the chip is recognized.
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