JP3530517B2 - Flip chip mounting device with alignment correction function - Google Patents

Flip chip mounting device with alignment correction function

Info

Publication number
JP3530517B2
JP3530517B2 JP2001399355A JP2001399355A JP3530517B2 JP 3530517 B2 JP3530517 B2 JP 3530517B2 JP 2001399355 A JP2001399355 A JP 2001399355A JP 2001399355 A JP2001399355 A JP 2001399355A JP 3530517 B2 JP3530517 B2 JP 3530517B2
Authority
JP
Japan
Prior art keywords
alignment
circuit board
flip
chip mounting
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2001399355A
Other languages
Japanese (ja)
Other versions
JP2003197682A (en
Inventor
直人 中谷
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Avionics Co Ltd
Original Assignee
Nippon Avionics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Avionics Co Ltd filed Critical Nippon Avionics Co Ltd
Priority to JP2001399355A priority Critical patent/JP3530517B2/en
Publication of JP2003197682A publication Critical patent/JP2003197682A/en
Application granted granted Critical
Publication of JP3530517B2 publication Critical patent/JP3530517B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54426Marks applied to semiconductor devices or parts for alignment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • H01L2223/5448Located on chip prior to dicing and remaining on chip after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75743Suction holding means
    • H01L2224/75745Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75753Means for optical alignment, e.g. sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/759Means for monitoring the connection process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112Aligning
    • H01L2224/81121Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01004Beryllium [Be]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01005Boron [B]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01033Arsenic [As]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は、半導体チップと回
路基板をフリップチップ実装する装置の、半導体チップ
と回路基板の位置合わせに関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to alignment of a semiconductor chip and a circuit board in an apparatus for flip-chip mounting a semiconductor chip and a circuit board.

【0002】[0002]

【従来の技術】近年、モバイル情報通信関連機器等では
回路基板のよりいっそうの小型化、軽量化、高周波化に
よる高性能化、コストダウンが切望されている。そのた
め、半導体チップと回路基板の直接実装が可能なフリッ
プチップ実装が有効となっている。また、半導体チップ
の小型化や高集積度化も進んでおり、これに伴ってフリ
ップチップ実装での電極パッドサイズの微細化や電極パ
ッド間ピッチの微細化も進んでいる。
2. Description of the Related Art In recent years, there has been a strong demand for further miniaturization and weight reduction of circuit boards in mobile information communication-related equipment and the like, higher performance due to higher frequencies, and cost reduction. Therefore, flip chip mounting, which enables direct mounting of a semiconductor chip and a circuit board, is effective. Further, miniaturization and high integration of semiconductor chips are also progressing, and along with this, miniaturization of electrode pad size in flip chip mounting and miniaturization of pitch between electrode pads are also progressing.

【0003】ここで、金−金接合に代表されるフリップ
チップ実装の多くは拡散接合であり、溶融接合であるは
んだ接合のようにセルフアライメント効果が得られない
ため、実装時の位置合わせの精度がそのままフリップチ
ップ実装の実装精度となる。
Most of flip-chip mounting represented by gold-gold bonding is diffusion bonding, and a self-alignment effect cannot be obtained unlike solder bonding which is fusion bonding, and therefore, positioning accuracy at the time of mounting is high. Becomes the mounting accuracy of flip chip mounting as it is.

【0004】実装時の位置合わせに用いられる回路基板
の位置合わせマーク(以下、「アライメントマーク」と
いう)は、通常は半導体チップが実装される実装エリア
の近傍でかつ実装エリアの外側にエッチングによって作
られることが多く、このエッチング液は撹拌のために一
定方向に流れているのが一般的である。
The alignment mark of the circuit board (hereinafter referred to as "alignment mark") used for alignment during mounting is usually formed by etching near the mounting area where the semiconductor chip is mounted and outside the mounting area. In many cases, the etching solution generally flows in a certain direction due to stirring.

【0005】しかし、回路基板のアライメントマークは
エッチング時のエッチング液の流れる方向等のエッチン
グファクタにより、特に20μm前後またはそれ以上の
導体厚を有する回路基板においては、アライメントマー
クが設計通りの形状にならず、アライメントマーク上面
からアライメントマーク形成面(下面)に到るに従って
形状がゆがんでしまうことがある。
However, the alignment mark on the circuit board depends on the etching factor such as the flowing direction of the etching solution at the time of etching. Especially, in the case of a circuit board having a conductor thickness of about 20 μm or more, the alignment mark does not have the designed shape. Instead, the shape may be distorted from the top surface of the alignment mark to the alignment mark formation surface (bottom surface).

【0006】[0006]

【発明が解決しようとする課題】このようなアライメン
トマークをカメラで撮像して重心点を求めると、設計上
の中心点とのずれが生じてしまう。また、このアライメ
ントマークのゆがみは回路基板の製造ロットによって同
じ傾向を示すため、回路基板の製造ロット全般に前述の
ずれが生じてしまい、この結果高精度なフリップチップ
実装が実現できないという問題がある。さらには前述の
ずれを見込んで電極パッドサイズと電極パッド間ピッチ
を定めなければならず、電極パッドサイズの微細化と電
極パッド間ピッチの微細化の妨げにもなるという問題も
ある。
If the center of gravity is obtained by imaging such an alignment mark with a camera, a deviation from the designed center point will occur. Further, since the distortion of the alignment mark shows the same tendency depending on the manufacturing lot of the circuit board, the above-mentioned deviation occurs in the whole manufacturing lot of the circuit board, and as a result, there is a problem that highly accurate flip chip mounting cannot be realized. . Further, the electrode pad size and the pitch between the electrode pads must be determined in consideration of the above-mentioned deviation, which causes a problem that the miniaturization of the electrode pad size and the miniaturization of the pitch between the electrode pads are hindered.

【0007】本発明は上記実状に鑑みてなされたもの
で、より高精度なフリップチップ実装を実現し、さらに
は電極パッドサイズの微細化と電極パッド間ピッチの微
細化を可能とするフリップチップ実装装置を提供するこ
とを目的とする。
The present invention has been made in view of the above-mentioned circumstances, and realizes a more accurate flip chip mounting, and further enables a finer electrode pad size and a finer pitch between electrode pads. The purpose is to provide a device.

【0008】[0008]

【課題を解決するための手段】前述の問題を解決すべ
く、本発明であるアライメント補正機能付きフリップチ
ップ実装装置は、接合面の電極パッドにバンプが形成さ
れた半導体チップを、電極パッドが形成された回路基板
に位置合わせしたのちフェースダウン実装するフリップ
チップ実装装置であって、半導体チップ上の少なくとも
2ヶ所のアライメントマークと、回路基板上の少なくと
も2ヶ所のアライメントマークをカメラで撮像し、該ア
ライメントマークの重心点のX座標及びY座標を求め、
この座標データを元に位置合わせを行ってフリップチッ
プ実装し、半導体チップのシリコン部分を透過する波長
の赤外光を検出する赤外線顕微鏡を用いて、該フリップ
チップ実装後の半導体チップのシリコン部分を透過撮像
することにより、該半導体チップ上の所定の少なくとも
2ヶ所の電極パッドと、これに対応する該回路基板上の
電極パッドを検出して比較することにより、X軸方向及
びY軸方向あるいはさらにθ軸方向のずれ量を求め、こ
のずれ量をその後の位置合わせでの補正値として利用す
ることを特徴としている。(請求項1記載の発明)
In order to solve the above-mentioned problems, a flip-chip mounting apparatus with an alignment correction function according to the present invention forms a semiconductor chip in which bumps are formed on electrode pads on a bonding surface by the electrode pads. A flip-chip mounting device for performing face-down mounting after aligning with a printed circuit board, wherein at least two alignment marks on the semiconductor chip and at least two alignment marks on the circuit board are imaged by a camera, Find the X and Y coordinates of the centroid of the alignment mark,
Flip-chip mounting is performed based on this coordinate data, and an infrared microscope that detects infrared light of a wavelength that passes through the silicon portion of the semiconductor chip is used to detect the silicon portion of the semiconductor chip after the flip-chip mounting. Through transmission imaging, at least two predetermined electrode pads on the semiconductor chip and the corresponding electrode pads on the circuit board are detected and compared to determine the X-axis direction and the Y-axis direction or further. The feature is that the shift amount in the θ-axis direction is obtained and this shift amount is used as a correction value in the subsequent alignment. (Invention according to claim 1)

【0009】[0009]

【発明の実施の形態】次に、本発明の実施の形態につい
て図面を参照して詳細に説明する。図1は、本アライメ
ント補正機能付きフリップチップ実装装置の説明図及び
機能ブロック図である。図2は、アライメントマークが
ゆがんだ場合のフリップチップ実装後の回路基板と半導
体チップを横から見た図である。図3は、図2を上から
赤外線顕微鏡で透視して撮像した場合の図である。図4
は、アライメントマークが設計通りの場合のフリップチ
ップ実装後の回路基板と半導体チップを横から見た図で
ある。図5は、図4を上から赤外線顕微鏡で透視して撮
像した場合の図である。
BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an explanatory diagram and a functional block diagram of the flip-chip mounting apparatus with the alignment correction function. FIG. 2 is a side view of the circuit board and the semiconductor chip after flip-chip mounting when the alignment mark is distorted. FIG. 3 is a diagram of a case where FIG. 2 is viewed through an infrared microscope and imaged. Figure 4
[FIG. 6] is a side view of the circuit board and the semiconductor chip after flip-chip mounting when the alignment mark is as designed. FIG. 5 is a diagram of a case where FIG. 4 is seen through with an infrared microscope and is imaged.

【0010】図1、図2、図3、図4、及び図5におい
て、10はシリコン基板上に回路を形成した半導体チッ
プ、11a及び11bは半導体チップ10のアライメン
トマーク、121…12nは半導体チップ10の電極パ
ッド、131…13nは半導体チップ10の電極パッド
121…12n上に形成した金バンプ、20は回路基
板、21a及び21bは回路基板20のアライメントマ
ーク、221…22nは回路基板20の電極パッド、2
31…23nは回路基板20の電極パッド221…22
nから続く配線パターン、30は回路基板20を保持す
る接合ステージ、31は位置合わせ時に半導体チップ1
0のアライメントマーク11a及び11b、回路基板2
0のアライメントマーク21a及び21bを撮像するカ
メラ、32は半導体チップ10と回路基板20の画像を
カメラ31で同時に重ねて撮像するためのビームスプリ
ッタ、33は半導体チップ10を保持する吸着ツール、
34は吸着ツール33を取り付け上下に昇降する昇降ア
ーム、35は昇降アーム34を駆動して半導体チップ1
0と回路基板20を接合する加圧部、36は半導体チッ
プ10接合後の回路基板20を保持する検査ステージ、
37は接合後の半導体チップ10のシリコン部分を透過
する波長900nm〜1200nmの赤外線を検出し、
半導体チップ10の電極パッド121…12nや回路基
板20の電極パッド221…22nを撮像する赤外線顕
微鏡、41はカメラ31で撮像した半導体チップ10の
アライメントマーク11a及び11b、回路基板20の
アライメントマーク21a及び21bの画像データを2
値化し重心点の座標を求めるカメラ画像処理部、47は
赤外線顕微鏡37で撮像した半導体チップ10の電極パ
ッド121及び12n、回路基板20の電極パッド22
1及び22nの画像データを2値化し重心点の座標を求
める赤外線画像処理部、48はカメラ画像処理部41で
求めたアライメントマーク11a、11b、21a及び
21bの重心点の座標と、赤外線画像処理部47で求め
た電極パッド121、12n、221及び22nの重心
点の座標から位置合わせのための演算を行う座標演算
部、49は加圧部35に対する加圧制御や接合ステージ
30または/及び加圧部35に対する位置合わせ制御を
行う制御部である。
1, FIG. 2, FIG. 3, FIG. 4, and FIG. 5, 10 is a semiconductor chip having a circuit formed on a silicon substrate, 11a and 11b are alignment marks of the semiconductor chip 10, and 121 ... 12n are semiconductor chips. 13n are gold bumps formed on the electrode pads 121 ... 12n of the semiconductor chip 10, 20 is a circuit board, 21a and 21b are alignment marks of the circuit board 20, 221 ... 22n are electrodes of the circuit board 20. Pads, 2
31 ... 23n are electrode pads 221 ... 22 of the circuit board 20.
n is a wiring pattern, 30 is a bonding stage that holds the circuit board 20, and 31 is the semiconductor chip 1 during alignment.
0 alignment marks 11a and 11b, circuit board 2
A camera for picking up the alignment marks 21a and 21b of 0, a beam splitter 32 for picking up images of the semiconductor chip 10 and the circuit board 20 at the same time by the camera 31, and a suction tool 33 for holding the semiconductor chip 10,
Reference numeral 34 is an elevating arm that attaches the suction tool 33 and moves up and down. Reference numeral 35 drives the elevating arm 34 and the semiconductor chip
0 is a pressurizing section for joining the circuit board 20, 36 is an inspection stage for holding the circuit board 20 after the semiconductor chip 10 is joined,
37 detects infrared rays having a wavelength of 900 nm to 1200 nm that pass through the silicon portion of the semiconductor chip 10 after bonding,
12n of the semiconductor chip 10 and the electrode pads 221 ... 22n of the circuit board 20. Reference numeral 41 denotes alignment marks 11a and 11b of the semiconductor chip 10 imaged by the camera 31, alignment marks 21a of the circuit board 20, and 21b image data 2
A camera image processing unit 47 for quantifying and calculating the coordinates of the center of gravity, 47 is the electrode pads 121 and 12n of the semiconductor chip 10 imaged by the infrared microscope 37, and the electrode pad 22 of the circuit board 20.
An infrared image processing unit for binarizing the image data of 1 and 22n to obtain the coordinates of the center of gravity, and 48 is the coordinates of the center of gravity of the alignment marks 11a, 11b, 21a and 21b obtained by the camera image processing unit 41, and the infrared image processing. A coordinate calculation unit that performs a calculation for alignment from the coordinates of the center of gravity of the electrode pads 121, 12n, 221 and 22n obtained by the unit 47, and 49 is the pressure control for the pressure unit 35 and / or the bonding stage 30 and / or the addition stage. It is a control unit that performs alignment control for the pressure unit 35.

【0011】図2及び図3のアライメントマーク21a
とアライメントマーク21bは、形状が設計値よりもX
軸上を左方向に伸びてしまった場合の例を示している。
尚、図2のアライメントマーク21aと21b内の点線
は設計通りだった場合の形状を示している。
The alignment mark 21a shown in FIG. 2 and FIG.
The shape of the alignment mark 21b and the alignment mark 21b is X
An example is shown in which the shaft extends to the left.
The dotted lines in the alignment marks 21a and 21b in FIG. 2 indicate the shapes as designed.

【0012】まず、図1において、吸着ツール33に半
導体チップ10を取り付け、接合ステージ30に回路基
板20を取り付ける。
First, in FIG. 1, the semiconductor chip 10 is attached to the suction tool 33, and the circuit board 20 is attached to the bonding stage 30.

【0013】次に、制御部49はカメラ31とビームス
プリッタ32を矢印の方向に移動させ、カメラ31で
回路基板20のアライメントマーク21a及び21bを
撮像する。カメラ画像処理部41にて撮像した画像デー
タを2値化すると、図3において斜線で塗り潰された部
分が検出できるので、これらの重心点のX座標及びY座
標を求める。また半導体チップ10のアライメントマー
ク11a及び11bについても、同様にカメラ画像処理
部41にて撮像した画像データを2値化し重心点のX座
標及びY座標を求める。これらの座標を元に座標演算部
48にて位置合わせの演算を行い、この演算結果を元に
制御部49が接合ステージ30または/及び加圧部35
をX軸方向及びY軸方向あるいはさらにθ軸方向に移動
させて位置合わせを行う。
Next, the control section 49 moves the camera 31 and the beam splitter 32 in the direction of the arrow so that the camera 31 images the alignment marks 21a and 21b of the circuit board 20. When the image data captured by the camera image processing unit 41 is binarized, the shaded areas in FIG. 3 can be detected, so the X and Y coordinates of these centroids are determined. Similarly, regarding the alignment marks 11a and 11b of the semiconductor chip 10, the image data captured by the camera image processing unit 41 is also binarized to obtain the X and Y coordinates of the center of gravity. Based on these coordinates, the coordinate calculation unit 48 calculates the position, and the control unit 49 controls the bonding stage 30 and / or the pressure unit 35 based on the calculation result.
Is moved in the X-axis direction and the Y-axis direction or further in the θ-axis direction to perform alignment.

【0014】上記回路基板20と半導体チップ10の位
置合わせの動作は、回路基板20を保持する接合ステー
ジ30、または吸着ツール33にて半導体チップ10を
保持する加圧部35の、いずれか一方または両方が協動
し、X軸方向及びY軸方向あるいはさらにθ軸方向に移
動することで行う。
The operation of aligning the circuit board 20 and the semiconductor chip 10 is carried out by either the bonding stage 30 holding the circuit board 20 or the pressing section 35 holding the semiconductor chip 10 by the suction tool 33, or Both of them work together to move in the X-axis direction and the Y-axis direction, or further in the θ-axis direction.

【0015】4ヶ所のアライメントマークの撮像完了
後、制御部49はカメラ31とビームスプリッタ32を
矢印の方向に移動させ元の位置に戻す。
After the image pickup of the four alignment marks is completed, the controller 49 moves the camera 31 and the beam splitter 32 in the directions of the arrows to return them to their original positions.

【0016】ここで、図3において、アライメントマー
ク21aの重心点の座標のずれの量は、設計上の位置か
らΔxma、Δymaである。同様に、アライメントマ
ーク21bの重心点の座標のずれの量は、設計上の位置
からΔxmb、Δymbである。しかし、これらのずれ
の量をフリップチップ実装前に正確に測定することは困
難であり、測定できたとしてもこのずれ量を用いて半導
体チップ10の位置を補正することは、この後の接合時
に機械的誤差がさらに生じるため得策ではないので、第
1回目は補正しない。
Here, in FIG. 3, the deviation amount of the coordinates of the center of gravity of the alignment mark 21a is Δxma and Δyma from the designed position. Similarly, the amount of deviation of the coordinates of the center of gravity of the alignment mark 21b is Δxmb and Δymb from the designed position. However, it is difficult to accurately measure the amount of these deviations before flip-chip mounting, and even if it is possible to correct the position of the semiconductor chip 10 using this deviation amount, it is necessary to correct the position at the time of subsequent bonding. Since it is not a good idea because mechanical error will occur further, it is not corrected in the first time.

【0017】位置合わせ完了後、制御部49は加圧部3
5に対し接合のための加圧(下降)を指示する。加圧部
35は昇降アーム34を矢印の方向に移動させ、回路
基板20に半導体チップ10をフリップチップ実装す
る。フリップチップ実装後、制御部49は吸着ツール3
3から半導体チップ10を取り外させ、さらに加圧部3
5に対し指示し昇降アームを矢印の方向に移動させ元
の位置に戻す。
After the alignment is completed, the control unit 49 controls the pressure unit 3
5 is instructed to pressurize (lower) for joining. The pressure unit 35 moves the elevating arm 34 in the direction of the arrow to flip-chip mount the semiconductor chip 10 on the circuit board 20. After the flip chip mounting, the control unit 49 controls the suction tool 3
3, the semiconductor chip 10 is removed, and the pressing unit 3
Instruct to 5 and move the lifting arm in the direction of the arrow to return it to the original position.

【0018】第1回目のフリップチップ実装後、回路基
板20を図1において矢印の方向の検査ステージ36
に移送し、半導体チップ10のシリコン部分を透過して
撮像可能な赤外線顕微鏡37を用いて、半導体チップ1
0上の所定の2ヶ所の電極パッド121及び12nと、
これに対応する回路基板20上の2ヶ所の電極パッド2
21及び22nを撮像する。赤外線画像処理部47にて
撮像した画像データを2値化し、合計4ヶ所の重心点の
X座標及びY座標を求める。
After the first flip-chip mounting, the circuit board 20 is mounted on the inspection stage 36 in the direction of the arrow in FIG.
To the semiconductor chip 1 by using the infrared microscope 37 capable of being imaged through the silicon portion of the semiconductor chip 10.
0 two predetermined electrode pads 121 and 12n,
Corresponding to this, two electrode pads 2 on the circuit board 20
21 and 22n are imaged. The image data captured by the infrared image processing unit 47 is binarized, and the X coordinate and the Y coordinate of the total of four centroids are obtained.

【0019】ここで上記回路基板20の移送は、接合ス
テージ30が回路基板20を保持したまま検査ステージ
36の位置まで移動しても良いし、接合ステージ30か
ら回路基板20を取り外して検査ステージ36に新たに
取り付けても良い。
The circuit board 20 may be moved to the position of the inspection stage 36 while the bonding stage 30 holds the circuit board 20. Alternatively, the circuit board 20 may be removed from the bonding stage 30 and the inspection stage 36 may be moved. It may be newly attached to.

【0020】次に、座標演算部48にて半導体チップ1
0上の電極パッド121の重心点の座標と、対応する回
路基板20上の電極パッド221の重心点の座標から、
フリップチップ実装後の半導体チップ10の電極パッド
121の、本来の位置からのずれ、Δx1とΔy1を求
める。
Next, in the coordinate calculation unit 48, the semiconductor chip 1
From the coordinates of the center of gravity of the electrode pad 121 on 0 and the coordinates of the center of gravity of the corresponding electrode pad 221 on the circuit board 20,
The deviations Δx1 and Δy1 of the electrode pads 121 of the semiconductor chip 10 after flip-chip mounting from the original positions are obtained.

【0021】同様に、座標演算部48にて半導体チップ
10上の電極パッド12nの重心点の座標と、対応する
回路基板20上の電極パッド22nの重心点の座標か
ら、フリップチップ実装後の半導体チップ10の電極パ
ッド12nの、本来の位置からのずれ、ΔxnとΔyn
を求める。
Similarly, in the coordinate calculation unit 48, from the coordinates of the center of gravity of the electrode pad 12n on the semiconductor chip 10 and the coordinates of the center of gravity of the corresponding electrode pad 22n on the circuit board 20, the semiconductor after flip chip mounting is carried out. Deviation of the electrode pad 12n of the chip 10 from its original position, Δxn and Δyn
Ask for.

【0022】さらに、座標演算部48にてΔx1とΔy
1、ΔxnとΔynから、半導体チップ10の中心の本
来の位置からのずれ、Δx、Δy及びΔθを求める。
Further, the coordinate calculation unit 48 calculates Δx1 and Δy.
From 1, Δxn and Δyn, the deviation from the original position of the center of the semiconductor chip 10, Δx, Δy, and Δθ are obtained.

【0023】ここで、回路基板20のアライメントマー
ク21aと21bのゆがみが、回路基板20の製造ロッ
トによって同じ傾向を示すことを利用し、第2回目以降
のフリップチップ実装での位置合わせでは、座標演算部
48にて上で求めたΔx、Δy及びΔθの値を補正値と
して用いる。つまり回路基板20のアライメントマーク
21a及び21b、半導体チップ10のアライメントマ
ーク11a及び11bから求めた位置から、X座標方向
に−Δxだけずらし、Y座標方向に−Δyだけずらし、
θ座標方向に−Δθだけずらす(回転する)ことで、よ
り正確な位置合わせが可能となる。
Here, taking advantage of the fact that the distortions of the alignment marks 21a and 21b of the circuit board 20 show the same tendency depending on the manufacturing lot of the circuit board 20, the coordinates are used in the alignment in the second and subsequent flip-chip mounting. The values of Δx, Δy, and Δθ obtained above by the calculation unit 48 are used as correction values. That is, from the positions obtained from the alignment marks 21a and 21b of the circuit board 20 and the alignment marks 11a and 11b of the semiconductor chip 10, they are displaced by -Δx in the X coordinate direction and by -Δy in the Y coordinate direction,
By shifting (rotating) by −Δθ in the θ coordinate direction, more accurate alignment becomes possible.

【0024】上述の赤外線顕微鏡37を用いて求めた補
正値、Δx、Δy及びΔθは、第1回目のフリップチッ
プ実装後だけ求め、2回目以降の位置合わせ時には第1
回目の補正値を用いて補正しても良いが、可能であれ
ば、毎回求めるか、または回路基板20の製造ロットの
切り替わり直後に求め直し、次の位置合わせ時にはその
補正値で補正することが望ましい。
The correction values Δx, Δy and Δθ obtained by using the above infrared microscope 37 are obtained only after the first flip-chip mounting, and the first correction values are used for the second and subsequent alignments.
The correction may be performed using the correction value for the second time, but if possible, the correction value may be calculated each time, or may be calculated again immediately after the manufacturing lot of the circuit board 20 is switched, and the correction value may be used for the next alignment. desirable.

【0025】ここで、補正値を毎回求める方法は、時間
的なロスが発生するが、回路基板20の製造ロットを管
理する必要がないというメリットがあり、逆に、補正値
を回路基板20の製造ロットの切り替わり直後に求め直
す方法は、回路基板20の製造ロットを管理する必要が
あるが、時間的なロスが少なくて済むというメリットが
ある。
Here, the method of obtaining the correction value every time has a merit that it is not necessary to control the manufacturing lot of the circuit board 20 although a time loss occurs, and conversely, the correction value of the circuit board 20 is obtained. The method of re-obtaining immediately after changing the manufacturing lot requires management of the manufacturing lot of the circuit board 20, but has an advantage that time loss is small.

【0026】また、上述の位置合わせの補正は、人手に
よる手動入力で実施しても良いが、より良くは、人為的
な手間が不要でかつ入力ミスもない、自動で実施するこ
とが望ましい。
Further, the above-mentioned position adjustment may be carried out manually by manual input, but more preferably, it is preferably carried out automatically without human labor and without input error.

【0027】ここで、半導体チップ10上の所定の電極
パッド121と電極パッド12nの位置、及びこれに対
応する回路基板20上の電極パッド221と電極パッド
22nの位置は、半導体チップ10の対角線上に設定し
てできる限り長く距離をとり、より正確に測定できるよ
うにすることが望ましいことは言うまでもない。
The positions of the predetermined electrode pads 121 and the electrode pads 12n on the semiconductor chip 10 and the corresponding positions of the electrode pads 221 and 22n on the circuit board 20 are on the diagonal line of the semiconductor chip 10. Needless to say, it is desirable to set the distance to as long as possible so that the measurement can be performed more accurately.

【0028】[0028]

【発明の効果】以上説明したように、本発明のアライメ
ント補正機能付きフリップチップ実装装置によれば、ア
ライメントマークのゆがみによるフリップチップ実装で
の位置のずれ量、Δx、Δy及びΔθを求め、次回以降
のフリップチップ実装での位置合わせ時にこのずれ量を
補正することにより、より高精度なフリップチップ実装
が実現でき、さらには上記位置のずれ量を見込んで回路
基板の電極パッドサイズと電極パッド間ピッチを大きめ
に定める必要がなくなり、電極パッドサイズの微細化と
電極パッド間ピッチの微細化を可能とすることができ
る。(請求項1記載の発明)
As described above, according to the flip-chip mounting apparatus with the alignment correction function of the present invention, the positional deviation amount, Δx, Δy, and Δθ in the flip-chip mounting due to the distortion of the alignment mark is obtained, and next time Higher precision flip chip mounting can be realized by correcting this misalignment amount during alignment in the subsequent flip chip mounting. Furthermore, in consideration of the above misalignment amount, the electrode pad size of the circuit board and the gap between the electrode pads can be estimated. It is not necessary to set a large pitch, and it is possible to reduce the size of the electrode pads and the pitch between the electrode pads. (Invention according to claim 1)

【0029】また、直前のフリップチップ実装結果のず
れ量を毎回求め、次の位置合わせ時に補正値として利用
することで、回路基板の製造ロットの切り替わりを管理
することなく、より高精度なフリップチップ実装が可能
となる。(請求項2記載の発明)
Further, by obtaining the deviation amount of the immediately preceding flip chip mounting result each time and using it as the correction value at the time of the next alignment, the flip chip with higher precision can be realized without controlling the change of the manufacturing lot of the circuit board. Can be implemented. (Invention of Claim 2)

【0030】また、回路基板の製造ロットの切り替わり
直後に補正値を求め直し、この補正値を回路基板の製造
ロット毎の共通値として利用することで、時間的なロス
が少なく、より高精度なフリップチップ実装が可能とな
る。(請求項3記載の発明)
Further, by re-calculating the correction value immediately after the change of the circuit board manufacturing lot and using this correction value as a common value for each circuit board manufacturing lot, there is less time loss and higher accuracy. Flip chip mounting is possible. (Invention of Claim 3)

【0031】さらに、補正値を自動的に取り込んで利用
することで、人為的な手間が不要でかつ入力ミスもな
く、より高精度なフリップチップ実装が可能となる。
(請求項4記載の発明)
Further, since the correction value is automatically fetched and used, it is possible to perform flip chip mounting with higher accuracy, without requiring any manual labor and without input error.
(Invention of Claim 4)

【図面の簡単な説明】[Brief description of drawings]

【図1】 本アライメント補正機能付きフリップチップ
実装装置の説明図及び機能ブロック図である。
FIG. 1 is an explanatory diagram and a functional block diagram of a flip-chip mounting apparatus with an alignment correction function.

【図2】 アライメントマークがゆがんだ場合のフリッ
プチップ実装後の回路基板と半導体チップを横から見た
図である。
FIG. 2 is a side view of the circuit board and the semiconductor chip after flip-chip mounting when the alignment mark is distorted.

【図3】 図1を上から赤外線顕微鏡で透視して見た場
合の図である。
FIG. 3 is a diagram when FIG. 1 is seen through from above with an infrared microscope.

【図4】 アライメントマークが設計通りの場合のフリ
ップチップ実装後の回路基板と半導体チップを横から見
た図である。
FIG. 4 is a side view of the circuit board and the semiconductor chip after flip-chip mounting when the alignment mark is as designed.

【図5】 図3を上から赤外線顕微鏡で透視して見た場
合の図である。
FIG. 5 is a diagram when FIG. 3 is seen through with an infrared microscope from above.

【符号の説明】[Explanation of symbols]

10 …半導体チップ 11a…半導体チップのアライメントマークa 11b…半導体チップのアライメントマークb 121…半導体チップの電極パッド1 12n…半導体チップの電極パッドn 13 …金バンプ 20 …回路基板 21a…回路基板のアライメントマークa 21b…回路基板のアライメントマークb 221…回路基板の電極パッド1 22n…回路基板の電極パッドn 23 …配線パターン 30 …接合ステージ 31 …カメラ 32 …ビームスプリッタ 33 …吸着ツール 34 …昇降アーム 35 …加圧部 36 …検査ステージ 37 …赤外線顕微鏡 41 …カメラ画像処理部 47 …赤外線画像処理部 48 …座標演算部 49 …制御部 10 ... Semiconductor chip 11a ... Alignment mark a of semiconductor chip 11b ... Alignment mark b of semiconductor chip 121 ... Electrode pad 1 of semiconductor chip 12n ... Electrode pad n of semiconductor chip 13 ... Gold bump 20 ... Circuit board 21a ... Alignment mark a on the circuit board 21b ... Alignment mark b on the circuit board 221 ... Electrode pad 1 of the circuit board 22n ... Electrode pad n of the circuit board 23 ... Wiring pattern 30 ... Joining stage 31 ... Camera 32 ... Beam splitter 33… Suction tool 34 ... Lifting arm 35 ... Pressurizing unit 36 ... Inspection stage 37 ... Infrared microscope 41 ... Camera image processing unit 47 ... Infrared image processing unit 48 ... Coordinate calculation unit 49 ... Control unit

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 接合面の電極パッドにバンプが形成され
た半導体チップを、電極パッドが形成された回路基板に
位置合わせしたのちフェイスダウン実装するフリップチ
ップ実装装置であって、 半導体チップ上の少なくとも2ヶ所のアライメントマー
クと、回路基板上の少なくとも2ヶ所のアライメントマ
ークをカメラで撮像し、該アライメントマークの重心点
のX座標及びY座標を求め、この座標データを元に位置
合わせを行ってフリップチップ実装し、 半導体チップのシリコン部分を透過する波長の赤外光を
検出する赤外線顕微鏡を用いて、該フリップチップ実装
後の半導体チップのシリコン部分を透過撮像することに
より、該半導体チップ上の所定の少なくとも2ヶ所の電
極パッドと、これに対応する該回路基板上の電極パッド
を検出して比較することにより、X軸方向及びY軸方向
あるいはさらにθ軸方向のずれ量を求め、このずれ量を
その後の位置合わせでの補正値として利用することを特
徴とするアライメント補正機能付きフリップチップ実装
装置。
1. A flip-chip mounting apparatus for aligning a semiconductor chip having a bump formed on an electrode pad on a bonding surface with a circuit board having an electrode pad and then performing face-down mounting, at least on a semiconductor chip. The two alignment marks and at least two alignment marks on the circuit board are imaged by a camera, the X and Y coordinates of the center of gravity of the alignment marks are obtained, and alignment is performed based on this coordinate data and flipped. A chip is mounted and a silicon part of the semiconductor chip after the flip-chip mounting is transparently imaged by using an infrared microscope that detects infrared light having a wavelength that passes through the silicon part of the semiconductor chip. Of at least two electrode pads and the corresponding electrode pads on the circuit board are detected. Flip-chip mounting with an alignment correction function characterized by obtaining a displacement amount in the X-axis direction and the Y-axis direction or further in the θ-axis direction by comparison, and using this displacement amount as a correction value in the subsequent alignment. apparatus.
【請求項2】 前記補正値は、直前のフリップチップ実
装結果のずれ量を毎回求め、補正値として利用すること
を特徴とする請求項1記載のアライメント補正機能付き
フリップチップ実装装置。
2. The flip-chip mounting apparatus with an alignment correction function according to claim 1, wherein the correction value is used as a correction value by obtaining the deviation amount of the immediately preceding flip-chip mounting result each time.
【請求項3】 前記補正値は、前記回路基板の製造ロッ
トの切り替わり直後に求め直し、この補正値を前記製造
ロット毎の共通値として利用することを特徴とする請求
項1記載のアライメント補正機能付きフリップチップ実
装装置。
3. The alignment correction function according to claim 1, wherein the correction value is re-obtained immediately after the manufacturing lot of the circuit board is switched, and the correction value is used as a common value for each manufacturing lot. Flip chip mounting device.
【請求項4】 2回目以降の位置合わせ動作は、前記補
正値を自動的に取り込んで利用するようにプログラミン
グされた位置合わせ動作であることを特徴とする請求項
1から請求項3のいずれかに記載のアライメント補正機
能付きフリップチップ実装装置。
4. The alignment operation after the second alignment operation is a alignment operation programmed so as to automatically capture and use the correction value. Flip-chip mounting device with alignment correction function described in.
JP2001399355A 2001-12-28 2001-12-28 Flip chip mounting device with alignment correction function Expired - Fee Related JP3530517B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001399355A JP3530517B2 (en) 2001-12-28 2001-12-28 Flip chip mounting device with alignment correction function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001399355A JP3530517B2 (en) 2001-12-28 2001-12-28 Flip chip mounting device with alignment correction function

Publications (2)

Publication Number Publication Date
JP2003197682A JP2003197682A (en) 2003-07-11
JP3530517B2 true JP3530517B2 (en) 2004-05-24

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Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Link
JP (1) JP3530517B2 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3956903B2 (en) 2003-06-09 2007-08-08 セイコーエプソン株式会社 Semiconductor module, electronic device, and method for manufacturing semiconductor module
US7951648B2 (en) * 2008-07-01 2011-05-31 International Business Machines Corporation Chip-level underfill method of manufacture
JP5779386B2 (en) * 2011-04-19 2015-09-16 富士機械製造株式会社 Electrical component mounting machine
JP5876000B2 (en) 2012-06-11 2016-03-02 株式会社新川 Bonding apparatus and bonding method
JP6264760B2 (en) * 2012-07-06 2018-01-24 Tdk株式会社 Mounting method and mounting apparatus
CN113013285A (en) * 2021-01-26 2021-06-22 中国科学院上海技术物理研究所 Process method for correcting errors of reverse welding process system of focal plane detector
CN117080095B (en) * 2023-10-12 2024-01-23 江苏中科智芯集成科技有限公司 Wafer fan-out packaging method and packaging equipment

Also Published As

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