JP3284048B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device for flip-chip connecting a semiconductor element and a mounting board thereof using a solder bump electrode, and a method of manufacturing the same.

[0002]

2. Description of the Related Art It is known that a semiconductor element is flip-chip connected to a mounting substrate as a mounting means for miniaturizing and configuring a semiconductor circuit device. For example, as shown in FIG.
1, 332.. Are electrically and mechanically connected to each other. That is, a plurality of bump electrodes protrudingly formed so as to be connected to the circuit network of the mounting board 31, and corresponding to the terminal portions of the circuit constituting the semiconductor element 32,
The plurality of bump electrodes protrudingly formed on the surface are aligned and set to face each other, and the semiconductor element 12 is pressed against the mounting substrate 31 to temporarily join the facing bump electrodes. Thereafter, the bumps 331, 332,... Are formed by reflowing and melting and integrating the temporarily bonded bump electrodes.

Therefore, when such a mounting substrate 31 and a semiconductor element 32 are flip-chip connected, the positional relationship between the bump electrodes formed on the mounting substrate 31 and the bump electrodes formed on the semiconductor element 32 must be determined. It is necessary that the correspondence is matched, and it is necessary to align the mounting substrate 31 and the semiconductor element so that these bump electrodes are accurately opposed to each other during the connection operation.

FIG. 5A shows a mounting substrate 31 on which such flip-chip connection is performed. On the surface of the mounting substrate 31, an elongated metal wiring 341 corresponding to a position where a bump electrode is to be formed, Are formed, and an insulating layer 35 made of solder resist or the like is formed thereon. A groove-shaped opening 36 is formed in the insulating layer 34 so as to intersect with the metal wirings 341, 342,. You.

In the mounting board 31 configured as described above,
Pads 371 for forming bump electrodes at the intersections of the metal wirings 341, 342,.
372, ... The mounting board 31 has a position different from those of the metal wirings 341, 342,... And the opening 36, for example, an alignment mark 38 such as a cross mark.
Are formed. This alignment mark 38 is a metal wiring
Are formed at the same time as the formation of 341, 342,..., And the relative positional relationship with each of the metal wirings 341, 342,.

However, when such a mounting board 31 is manufactured, a step of forming the metal wirings 341, 342,... And a step of forming the groove-shaped opening 36 are performed in different steps. As shown in B), an opening 36 is formed at a position deviated from the original position shown by the broken line, and the opening 36 and the metal wirings 341 and 34 are formed.
The mutual positional relationship between 2 ... may be shifted. In such a case, the position of the bump electrode to be formed is naturally set to be shifted in the relative positional relationship with the alignment mark 38.

Therefore, even if the mounting substrate 31 and the semiconductor element 32 are aligned using the alignment mark 38, the position of the bump electrode formed on the semiconductor element 32 and the position of the bump electrode formed on the mounting substrate can be reduced. Do not match, making it difficult to connect flip-chips with high accuracy and reliability.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and it has been found that a mounting substrate having a plurality of bump electrodes and a semiconductor element having the same plurality of bump electrodes can be accurately aligned. Accordingly, it is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, in which flip-chip connection is performed with high accuracy and reliability thereof is reliably maintained.

[0009]

According to the present invention, there is provided a semiconductor device in which a semiconductor element is flip-chip connected to a mounting substrate via solder bumps.
Metal wiring is formed on the surface of the mounting substrate by a conductive material, and a groove-shaped opening is formed in the insulating layer formed on the surface of the mounting substrate so as to intersect with the metal wiring. A bump electrode is formed on the mounting portion, and a first material is formed on the mounting substrate using the same material as the material forming the metal wiring.
And a second alignment mark formed by using an insulating layer so as to partially overlap the first alignment mark. Here, the first and second alignment marks are each formed in a shape having a plurality of corner portions.

Further, in such a method of manufacturing a semiconductor device, the mounting substrate is provided with a first alignment mark formed of the same material as the metal wiring, and an opening formed in the insulating layer. Using the formed second alignment mark, the relative displacement is detected, the position of the solder bump electrode formed at the intersection of the groove-shaped opening and the metal wiring is determined, and the flip-chip connection is determined. Positioning correction is performed.

In the semiconductor device and the method of manufacturing the semiconductor device having the above-described structure, when a positional shift occurs between the metal wiring and the opening formed in the insulating layer, the first alignment mark and the first alignment mark are not aligned. The relative position with respect to the second alignment mark also shifts at the same time, and accordingly, a shift also occurs in the overlapping portion between the first and second alignment marks. Here, by configuring these alignment marks in a shape having a plurality of corners such as a square, for example, a relative displacement can be detected by detecting the corners. The alignment correction of the flip chip connection is easily and accurately performed.

[0012]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a mounting substrate 11 to which a semiconductor element is flip-chip connected as viewed from a plane. The mounting substrate 11 is formed of, for example, a glass substrate, an alumina substrate A1N substrate, or the like. Correspond to the positions where the bump electrodes are to be formed, respectively, metal wiring 121 of copper or tungsten material,
122 are formed.

An insulating layer 13 made of a solder resist, alumina, or the like is further formed on the surface of the mounting substrate 11. The insulating layer 13 has grooves formed so as to intersect with the metal wirings 121, 122,. The opening 14 is formed. The intersections between the openings 14 and the metal wirings 121, 122,... Are pads 151, 152,... For flip-chip connection.
2, the solder bump electrodes are formed so as to protrude from the portions.

Further, on the surface of the mounting substrate 11, for example, a first alignment mark 16 having a square shape is formed by the same material as the metal material constituting the metal wirings 121, 122,. A second alignment mark 17 is also formed by a square opening.
The first alignment mark 16 is formed simultaneously with the metal wirings 121, 122,..., And the second alignment mark 17 is formed simultaneously with the opening.

Here, it is effective to apply gold plating to the alignment marks 16 and 17 in order to facilitate optical detection and recognition. Although the shape is shown as a square in this figure, any shape having a plurality of corners such as a triangle and a cross mark can be used effectively.

In such a mounting board 11, the metal wiring 12
, And the step of forming the opening 14 in the insulating layer 13 are performed in separate steps, each of which is performed by aligning a predetermined mask on the substrate 11 and overlapping them. However, the metal wiring 121 in such a manufacturing process,
, And the opening 14 are not always coincident with each other, and there may be a positional displacement between them.

For example, as shown in FIG.
, 122 and the first alignment mark 16, the insulating layer 13 is formed according to a predetermined pattern, and the opening 14 and the second alignment mark 17 are formed in the insulating layer 13. In such a manufacturing process, the opening 14 of the insulating layer 13 which should be formed at the position indicated by the broken line may be formed with a shift with respect to each of the metal wirings 121, 122,. If the relative positional relationship between the wirings 121, 122,... And the opening 14 deviates, the positions of the pads 151, 152,. Therefore, even if bump electrodes made of solder are formed on each of the pads 151, 152,... In which such displacement has occurred, the relative positions of these bump electrodes are different from those of the bump electrodes formed on the semiconductor element. ing.

The alignment between the mounting board 11 and the semiconductor element is performed by the first and second alignment marks 16 and
For example, the position of the semiconductor element opposed to the mounting substrate 11 is corrected by using 17 so that the bump electrodes can be accurately opposed to each other.

Here, the first alignment mark 16 is formed simultaneously with the metal wirings 121, 122,..., And the second alignment mark 17 is formed simultaneously with the opening 14. Therefore, when the relative positional relationship between the metal wirings 121, 122,... And the opening 14 is shifted, the relative positional relationship between the first alignment mark 16 and the second alignment mark 17 is also shifted.

In the first and second alignment marks 16 and 17, one corner A of the first alignment mark 16 overlapping each other is defined as a first detection point,
Further, one corner B of the second alignment mark 17 is assumed to be a second detection point. When mounting the semiconductor element on the mounting board 11, the first and second
The detection points A and B of the alignment marks 16 and 17 are detected by optical means, and their mutual positional relationship is observed.

By recognizing the positional relationship between the first and second detection points A and B in this manner, the pads 151, 152,.
Is recognized, and the result of the recognition is fed back to the alignment process between the semiconductor element and the mounting substrate 11.
That is, the bump electrodes formed corresponding to the pads 151, 152,... Of the mounting substrate 11 and the bump electrodes formed on the semiconductor element are respectively aligned with high precision, and the flip chip connection process is performed. And the yield is effectively improved.

FIG. 3 particularly illustrates a second embodiment of the alignment mark portion. The first alignment mark 16 made of the same metal material and formed at the same time as the metal wirings 121, 122,. A second alignment mark 171 made of an insulating layer is formed so that the first and second alignment marks 16 and 171 partially overlap each other. Even when the second alignment mark 171 made of the insulating layer is formed at the same time as the insulating layer in which the opening 14 is formed, the pads 151, 152,..., As in the first embodiment. Can be recognized,
The yield of flip chip connection is improved.

[0023]

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, the displacement of the pad for forming the bump electrode formed on the mounting substrate to which the semiconductor element is connected is accurately determined. The result of the recognition is fed back to the alignment process between the semiconductor element and the mounting board, so that the yield of flip-chip connection is greatly improved and its reliability is also improved.

[Brief description of the drawings]

FIG. 1 is a plan view illustrating a mounting substrate of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a view for explaining a state of displacement on the mounting board.

FIG. 3 is a view for explaining a second embodiment of the semiconductor device, particularly showing an alignment mark portion.

FIG. 4 is a diagram illustrating flip-chip connection.

FIG. 5A is a plan view illustrating a mounting substrate used for a conventional flip chip connection, and FIG. 5B is a diagram illustrating a state of the same positional shift.

[Explanation of symbols]

11 mounting board, 121, 122, metal wiring, 13 insulating layer,
14 ... opening, 151, 152 ... pad, 16 ... first alignment mark, 17, 171 ... second alignment mark.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Hiroshi Tazawa 1 Toshiba-cho, Komukai-shi, Kawasaki-shi, Kanagawa Prefecture Inside the R & D Center of Toshiba Corporation (72) Inventor Naohiko Hirano Toshiba-cho, Komukai-ku, Kawasaki-shi, Kanagawa No. 1 Toshiba R & D Center Co., Ltd. (72) Inventor Tomoaki Takubo No. 1 Komukai Toshiba-cho, Yuki-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center (72) Inventor Ko-ichi Magome Horikawa-cho, Yuki-ku, Kawasaki-shi, Kanagawa No. 580 No. 1 Toshiba Semiconductor System Technology Center Co., Ltd. (72) Inventor Yoichi Hiruda No. 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki-shi, Kanagawa Prefecture Toshiba R & D Center Co., Ltd. (72) Inventor Koji Shibasaki Kawasaki-shi, Kanagawa 25-1, Ekimae Honmachi, Kawasaki-ku In-house Toshiba Microelectronics Corporation (56) References -102339 (JP, A) JitsuHiraku Akira 55-14712 (JP, U) (58 ) investigated the field (Int.Cl. ^7, DB name) H01L 21/60

Claims (5)

(57) [Claims] 1. A semiconductor device in which a semiconductor element is flip-chip connected to a mounting substrate via solder bumps, wherein a metal wiring formed of a conductive material on a surface of the mounting substrate, and a metal wiring formed on a surface of the mounting substrate. A groove-shaped opening formed in the insulating layer so as to intersect with the metal wiring, an electrode pad formed at an intersection of the metal wiring with the opening, and forming the metal wiring on the mounting substrate. A first alignment mark formed of the same material as the material, and a second alignment mark formed using the insulating layer so as to partially overlap the first alignment mark; A bump electrode is formed on each of the pad portions, and a displacement of the bump electrode is recognized by recognizing a displacement of the first and second alignment marks. A semiconductor device characterized in that feedback can be made to a subsequent process. 2. The semiconductor device according to claim 1, wherein said second alignment mark is constituted by an opening formed in said insulating layer simultaneously with said groove-shaped opening. 3. The semiconductor device according to claim 1, wherein said second alignment mark is constituted by an insulating layer in which said groove-shaped opening is formed. 4. The semiconductor device according to claim 1, wherein said first and second alignment marks are each formed in a shape having a plurality of corner portions. 5. A method of manufacturing a semiconductor device in which a semiconductor element is flip-chip connected to a mounting substrate via solder bumps, wherein the mounting substrate includes a metal wiring made of a conductive material formed on a surface thereof, An insulating layer having a groove-shaped opening formed so as to intersect with the metal wiring, and further formed of the same material as the material forming the metal wiring to form a first alignment mark and an insulating layer. A second alignment mark formed by utilizing the first alignment mark and a second alignment mark, and detecting a relative displacement between the first alignment mark and the second alignment mark, Wherein the position of the solder bump electrode formed at the intersection of the opening and the metal wiring is determined to correct the alignment of the flip-chip connection. Production method.