JPS6489668A - Convolution circuit - Google Patents

Abstract

PURPOSE:To speed up the processing of a convolutional operation by hardware- processing it as considering n-pieces of signals to be parallel signal when the convolutional operation is performed between n-pieces of consecutive one- dimensional binarization picture signals and the signal following said signal. CONSTITUTION:Consecutive 8 pieces of picture element signals x0-x7 (x0 is the latest signal) are inputted from 8 pieces of input terminals as synchronizing with the same clock signal, and x0-x2 among them are held by DFFs 21-23 for one clock period. Then, these signals x0-x7 and the signals x0'-x2', which are outputted from the DFFs 21-23 and are the signals x0-x2 one clock before, are supplied to four-input exclusive OR circuits 30-37, and the convolutional operation is performed by the fact that an exclusive OR operation is given to 4 pieces of the consecutive signals. Thus, since parallel input/output processing is performed in one clock, the convolutional operation can be performed at high speed.