JPS56161718A - Binary circuit for picture signal - Google Patents
Binary circuit for picture signalInfo
- Publication number
- JPS56161718A JPS56161718A JP6476780A JP6476780A JPS56161718A JP S56161718 A JPS56161718 A JP S56161718A JP 6476780 A JP6476780 A JP 6476780A JP 6476780 A JP6476780 A JP 6476780A JP S56161718 A JPS56161718 A JP S56161718A
- Authority
- JP
- Japan
- Prior art keywords
- picture signal
- terminal
- level
- analog
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
- H04N1/40—Picture signal circuits
- H04N1/403—Discrimination between the two tones in the picture signal of a two-tone original
Landscapes
- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Signal Processing (AREA)
- Image Input (AREA)
- Facsimile Image Signal Circuits (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To obtain the most suited reproduced picture, even if the contrast of an original is changed, by storing a picture signal in an analog register to detect the maximum/minimum levels, and making binarization through the voltage divided value taken as a threshold value. CONSTITUTION:An analog picture signal having levels according to the contrast of an original is inputted to the input terminal of an analog shift register 14 from an input terminal 13. Shift clocks are fed to the clock terminal of the shift register 14 from a terminal 15, and a picture signal inputted to the shift register 14 is sequentially transferred. Further, a maximum level is outputted at a terminal 17 of a level detection circuit 16 and a minimum level is outputted to a terminal 18, and the level of the output of an output terminal 25 of a voltage dividing circuit 24 is always at an intermediate level, even if the picture signal is greater or smaller. The picture signal picked up from an intermediate tap 1i of the shaft register 14 is binarized by a comparator 28 by taking this intermediate level as a threshold value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6476780A JPS56161718A (en) | 1980-05-15 | 1980-05-15 | Binary circuit for picture signal |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6476780A JPS56161718A (en) | 1980-05-15 | 1980-05-15 | Binary circuit for picture signal |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56161718A true JPS56161718A (en) | 1981-12-12 |
Family
ID=13267665
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6476780A Pending JPS56161718A (en) | 1980-05-15 | 1980-05-15 | Binary circuit for picture signal |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56161718A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02199923A (en) * | 1989-01-27 | 1990-08-08 | Nippon Telegr & Teleph Corp <Ntt> | Binarizing method for analog signal |
JPH04152699A (en) * | 1990-10-17 | 1992-05-26 | Juki Corp | Chip mounter |
-
1980
- 1980-05-15 JP JP6476780A patent/JPS56161718A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02199923A (en) * | 1989-01-27 | 1990-08-08 | Nippon Telegr & Teleph Corp <Ntt> | Binarizing method for analog signal |
JPH04152699A (en) * | 1990-10-17 | 1992-05-26 | Juki Corp | Chip mounter |
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