JPS57140044A - Digital mobile communication system - Google Patents
Digital mobile communication systemInfo
- Publication number
- JPS57140044A JPS57140044A JP56025959A JP2595981A JPS57140044A JP S57140044 A JPS57140044 A JP S57140044A JP 56025959 A JP56025959 A JP 56025959A JP 2595981 A JP2595981 A JP 2595981A JP S57140044 A JPS57140044 A JP S57140044A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- status
- base station
- mobile station
- repetitive pattern
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
- Mobile Radio Communication Systems (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
- Dc Digital Transmission (AREA)
Abstract
PURPOSE:To prevent malfunction due to detouring transmission and reception, by making a repetitive pattern of a signal for loop check from a base station to a mobile station different from that from the mobile station to the base station. CONSTITUTION:A signal for loop check LC from a base station to a mobile station is denoted as repetitive pattern of 1100, and the LC signal from the mobile station to the base station is denoted as repetitive pattern of 1, 0. The repetitive signal of 1100 inputted to a terminal IN is delayed at a 1-bit delay circuit 1, and inputted to an exclusive logical sum circuit 2 together with an input signal. The output of the circuit 2 is a repetitive pattern of 1, 0, and this signal is inputted to a part-bit status discriminating means consisting of a shift register 3, inverters 4a and 4b, AND circuits 5a and 5b, a monostable multivibrator 9, a frequency divider 8 and a CPU6, and the status of the register 3 is read in every 2 bits. The CPU6 counts the output of the circuits 5a and 5b to obtain the number (a) with the status of 1, 0 and the number (b) with the status of 0, 1, and the absolute value of (a)-(b) is compared with the reference value to discriminate the reception and nonreception.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025959A JPS5928097B2 (en) | 1981-02-24 | 1981-02-24 | Digital mobile communication system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP56025959A JPS5928097B2 (en) | 1981-02-24 | 1981-02-24 | Digital mobile communication system |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57140044A true JPS57140044A (en) | 1982-08-30 |
JPS5928097B2 JPS5928097B2 (en) | 1984-07-10 |
Family
ID=12180278
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP56025959A Expired JPS5928097B2 (en) | 1981-02-24 | 1981-02-24 | Digital mobile communication system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5928097B2 (en) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS59174485A (en) * | 1983-03-14 | 1984-10-02 | 株式会社 サタケ | Device for closing shutter |
JPS63131996U (en) * | 1987-02-23 | 1988-08-29 |
-
1981
- 1981-02-24 JP JP56025959A patent/JPS5928097B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5928097B2 (en) | 1984-07-10 |
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