JPS6450639A - Clock recovery device - Google Patents

Abstract

PURPOSE:To obtain a synchronization recovery clock with simple circuit constitution by providing a counter circuit in free-running at a lower frequency than that of a clock used for a sender side sending a transmission signal and resetting the counter circuit based on an edge of a set digital signal. CONSTITUTION:A reference clock S6 is given to a clock terminal CK of a counter 2 and an output subject to 1/256 frequency division is outputted as a recovery clock S5 from an output terminal 6. Moreover, an output of the recovery clock S5 and the output subject to 1/128 frequency division are ANDed by an AND gate 41 and the output of the AND gate 41 is given to one input of a 2-input AND gate 42 as a reset mask signal S4. On the other hand, the transmission data is given to an edge detection section 3, from which an edge is detected and an edge signal S2 is obtained, and the result is given to the other input of a 2-input AND gate 42 included in a reset section 4. The reset mask signal S4 and the edge signal S2 are ANDed by the AND gate 42, from which a reset signal S3 is obtained and it is given to a reset terminal R of the counter 2.