JPS56129445A - Simple signal transmission system - Google Patents

Simple signal transmission system

Info

Publication number
JPS56129445A
JPS56129445A JP3427380A JP3427380A JPS56129445A JP S56129445 A JPS56129445 A JP S56129445A JP 3427380 A JP3427380 A JP 3427380A JP 3427380 A JP3427380 A JP 3427380A JP S56129445 A JPS56129445 A JP S56129445A
Authority
JP
Japan
Prior art keywords
switch circuit
reception
synchronizing
input signal
transmission
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3427380A
Other languages
Japanese (ja)
Inventor
Kiyomi Fujita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3427380A priority Critical patent/JPS56129445A/en
Publication of JPS56129445A publication Critical patent/JPS56129445A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Time-Division Multiplex Systems (AREA)

Abstract

PURPOSE:To pick up a plurality of output signals from two transmissiom lines, by synchronizing the scane timing of the transmission with reception switch circuits. CONSTITUTION:The oscillator 12 inputs the clock in count-down to the transmission switch circuit 11 with the counter 13 at all times, and the terminals of A, B...Z are scanned with the decoder in the switch circuit 11, and data is transmitted by scanning timing through searching the input signal. On the other hand, at the reception device side, the synchronism between the scanning speed of the transmission side switch circuit 11 and the reception switch circuit 21 is taken, and the synchronizing signal in synchronizing with the input signal A is transmitted, logical produt with the lock of the reception side oscillator 22 is taken with the gate 24, and the input signal of the counter 23 is obtained.
JP3427380A 1980-03-17 1980-03-17 Simple signal transmission system Pending JPS56129445A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3427380A JPS56129445A (en) 1980-03-17 1980-03-17 Simple signal transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3427380A JPS56129445A (en) 1980-03-17 1980-03-17 Simple signal transmission system

Publications (1)

Publication Number Publication Date
JPS56129445A true JPS56129445A (en) 1981-10-09

Family

ID=12409546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3427380A Pending JPS56129445A (en) 1980-03-17 1980-03-17 Simple signal transmission system

Country Status (1)

Country Link
JP (1) JPS56129445A (en)

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