JPS5559315A - Pulse generating device - Google Patents

Pulse generating device

Info

Publication number
JPS5559315A
JPS5559315A JP13281678A JP13281678A JPS5559315A JP S5559315 A JPS5559315 A JP S5559315A JP 13281678 A JP13281678 A JP 13281678A JP 13281678 A JP13281678 A JP 13281678A JP S5559315 A JPS5559315 A JP S5559315A
Authority
JP
Japan
Prior art keywords
pulse
circuit
counting
rise
subtraction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13281678A
Other languages
Japanese (ja)
Inventor
Shozo Shimizu
Kazuhiro Azuma
Yoshio Fujimaru
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP13281678A priority Critical patent/JPS5559315A/en
Publication of JPS5559315A publication Critical patent/JPS5559315A/en
Pending legal-status Critical Current

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  • Transmission And Conversion Of Sensor Element Output (AREA)

Abstract

PURPOSE: To avoid the disagreement between the display of the set dial and the actual count number by carrying out the counting at both the rise and fall of the output pulse sent from the detector.
CONSTITUTION: Pulse M for the addition/subtraction decision purpose is delivered via both circuits of AND and OR and thus delayed slightly in comparison with the counting output pulse F delivered via only the OR circuit. Thus pulse M is still at the "L" level at the rise point of output F to give the addition instead of the subtraction which should be originally given. To avoid this, delay circuit 20 comprising inverters 21 and 22, resistors 23 and 24 plus capacitor 25 is provided between OR circuit 8 to give a logic process to the output pulse of the detector and addition/subtraction counter circuit 13. As a result, pulse F is delayed by time t at the subtraction time and then supplied to circuit 13 sufficiently after the rise of pulse M. In such way, an assured counting is secured at both the rise and fall of the input pulse, thus avoiding the disagreement of the counting number.
COPYRIGHT: (C)1980,JPO&Japio
JP13281678A 1978-10-27 1978-10-27 Pulse generating device Pending JPS5559315A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13281678A JPS5559315A (en) 1978-10-27 1978-10-27 Pulse generating device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13281678A JPS5559315A (en) 1978-10-27 1978-10-27 Pulse generating device

Publications (1)

Publication Number Publication Date
JPS5559315A true JPS5559315A (en) 1980-05-02

Family

ID=15090232

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13281678A Pending JPS5559315A (en) 1978-10-27 1978-10-27 Pulse generating device

Country Status (1)

Country Link
JP (1) JPS5559315A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150863A (en) * 1982-03-03 1983-09-07 Fujitsu Ten Ltd Measurement of rotation for rotor
JP2010048801A (en) * 2008-07-23 2010-03-04 Denso Corp Signal processing circuit for rotation detecting device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58150863A (en) * 1982-03-03 1983-09-07 Fujitsu Ten Ltd Measurement of rotation for rotor
JP2010048801A (en) * 2008-07-23 2010-03-04 Denso Corp Signal processing circuit for rotation detecting device

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