JPS57207948A - Division counter circuit - Google Patents

Division counter circuit

Info

Publication number
JPS57207948A
JPS57207948A JP9336281A JP9336281A JPS57207948A JP S57207948 A JPS57207948 A JP S57207948A JP 9336281 A JP9336281 A JP 9336281A JP 9336281 A JP9336281 A JP 9336281A JP S57207948 A JPS57207948 A JP S57207948A
Authority
JP
Japan
Prior art keywords
circuit
counters
output
signal
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9336281A
Other languages
Japanese (ja)
Inventor
Yoshimitsu Fukuda
Kazuyuki Yano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Orient Watch Co Ltd
Original Assignee
Orient Watch Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Orient Watch Co Ltd filed Critical Orient Watch Co Ltd
Priority to JP9336281A priority Critical patent/JPS57207948A/en
Publication of JPS57207948A publication Critical patent/JPS57207948A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To simplify the circuit configuration and to construct the titled circuit with integrated circuits, by obtaining the AND of the output from a setter and the output of a counter, by using the logical signal as a quotient, and, at the same time, by resetting the counter by the logical signal.
CONSTITUTION: Counting outputs of counters 12 and 13 which count input pulse of dividents are inputted into setters 14 and 15 which set divisors, and, when a counted content of the counters 12 and 13 coincides with a divisor N, an H-level signal is outputted and the output of an AND circuit 16 is set to an H level. An impulse-type signal is outputted from an AND circuit 18 by inputting one side of the H-level signal into one input terminal of the And citcuit 18 through another AND circuit 17 and the other side of the H-level signal into the other terminal of the AND circuit 18 through a delay circuit, and the impulse-type signal is inputted into reset terminals of the counters 12 and 13, and then, counters 12 and 13 are reset at every N-pieces inputted pulses. Therefore, an input pulse is divided into N pieces and the output pulse CO becomes CO=CL/N.
COPYRIGHT: (C)1982,JPO&Japio
JP9336281A 1981-06-16 1981-06-16 Division counter circuit Pending JPS57207948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9336281A JPS57207948A (en) 1981-06-16 1981-06-16 Division counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9336281A JPS57207948A (en) 1981-06-16 1981-06-16 Division counter circuit

Publications (1)

Publication Number Publication Date
JPS57207948A true JPS57207948A (en) 1982-12-20

Family

ID=14080169

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9336281A Pending JPS57207948A (en) 1981-06-16 1981-06-16 Division counter circuit

Country Status (1)

Country Link
JP (1) JPS57207948A (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5475250A (en) * 1977-11-28 1979-06-15 Mitsubishi Electric Corp Digital division circuit

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5475250A (en) * 1977-11-28 1979-06-15 Mitsubishi Electric Corp Digital division circuit

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