JPS5563128A - Digital timer device - Google Patents

Abstract

PURPOSE: To secure a combined use of one unit of the input terminal for both the gate signal and the reset signal by installing the terminal to supply the gate signal, two units of the delay filter and the logic circuit each.

CONSTITUTION: The time base signal is sent to the count input terminal of counter circuit via gate circuit 14, and the contents of circuit 1 is sent to elapsed time display unit 2 to display the elapsed time as well as preset unit 3 to produce the time- up output after comparison with the numerical value set previously. The gate signal applied to terminal 11 is then applied to gate circuit 14 via delay filter 60 and reverse circuit 12 with no time base signal supplied to circuit 1. Thus the timer operation is stopped. At the same time, the output of filter 60 is supplied to gate circuit 15 via buffer 13 and delay filter 70. When the output of circuit 12 rises up, gate 15 opens to reset circuit 1. Thus both the pause and reset of the timer are applied at the rise and fall of the gate signal and through one input terminal to secure an easy use for the timer device.

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