JPS6486615A - Clocked inverter circuit - Google Patents

Abstract

PURPOSE:To quicken the circuit operation by connecting two series circuits each having two 1st switch means in series in parallel, connecting one terminal of a remaining conductor terminal and supplying an input signal and a clock signal respectively to 4 switch control terminals respectively thereby reducing parasitic capacitance. CONSTITUTION:When the logic level of a clock input signal at a clock signal input terminal CK is at H, MOSFETs P5, P8, N6, N7 are conductive and a signal with an inverted logic to that of the input signal at a signal input terminal A is outputted at a signal output terminal Y. On the other hand, with a logic level of a clock input signal supplied to the clock signal input terminal CK at L, the MOSFETs P5, P8, N6, N7 are cut off and the level of the signal output terminal Y goes to a high impedance. The operation as the clocked inverter is applied as above. Thus, the gate width of a TR is enough to be nearly a half, resulting that the parasitic capacitance is decreased and the difference between the maximum and minimum delay times is reduced.