JPS6485453A - Elastic memory circuit with scrambler function - Google Patents

Elastic memory circuit with scrambler function

Info

Publication number
JPS6485453A
JPS6485453A JP62240960A JP24096087A JPS6485453A JP S6485453 A JPS6485453 A JP S6485453A JP 62240960 A JP62240960 A JP 62240960A JP 24096087 A JP24096087 A JP 24096087A JP S6485453 A JPS6485453 A JP S6485453A
Authority
JP
Japan
Prior art keywords
data
memory
circuits
written
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62240960A
Other languages
Japanese (ja)
Other versions
JPH0465575B2 (en
Inventor
Tsukasa Kyohara
Toru Iwai
Masato Toyoda
Seiichi Yamano
Fumio Mano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Original Assignee
Nippon Telegraph and Telephone Corp
Oki Electric Industry Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp, Oki Electric Industry Co Ltd filed Critical Nippon Telegraph and Telephone Corp
Priority to JP62240960A priority Critical patent/JPS6485453A/en
Publication of JPS6485453A publication Critical patent/JPS6485453A/en
Publication of JPH0465575B2 publication Critical patent/JPH0465575B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Communication Control (AREA)
  • Bidirectional Digital Transmission (AREA)

Abstract

PURPOSE:To facilitate large scale integration and to remarkably reduce the number of circuits by providing an inverting means corresponding to the scramble pattern to input or output side of each memory cell. CONSTITUTION:A serial data inputted to a data input terminal 31 is written in one of 1st memory 30a-31st memory 30f given with a data latch signal from an address decoder circuit 34. Thus in reading the data written in the elastic memory 30, the clock given to a readout clock input terminal 35 is counted up by a readout counter 36. Based on the result of counting, the output of the 1st memory 30a-31st memory 30f is selected by a data selector circuit 37 and the data of the result of selection is outputted to a data output terminal 38. In this case, randomizing is applied by using an inverter 39 provided corresponding to the scramble pattern. Thus, the number of circuits is reduced remarkably and advantageous more than LSI.
JP62240960A 1987-09-28 1987-09-28 Elastic memory circuit with scrambler function Granted JPS6485453A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62240960A JPS6485453A (en) 1987-09-28 1987-09-28 Elastic memory circuit with scrambler function

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62240960A JPS6485453A (en) 1987-09-28 1987-09-28 Elastic memory circuit with scrambler function

Publications (2)

Publication Number Publication Date
JPS6485453A true JPS6485453A (en) 1989-03-30
JPH0465575B2 JPH0465575B2 (en) 1992-10-20

Family

ID=17067213

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62240960A Granted JPS6485453A (en) 1987-09-28 1987-09-28 Elastic memory circuit with scrambler function

Country Status (1)

Country Link
JP (1) JPS6485453A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012205676A (en) 2011-03-29 2012-10-25 Terumo Corp Sensor

Also Published As

Publication number Publication date
JPH0465575B2 (en) 1992-10-20

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