JPS6481253A - Package of semiconductor integrated circuit - Google Patents
Package of semiconductor integrated circuitInfo
- Publication number
- JPS6481253A JPS6481253A JP62238293A JP23829387A JPS6481253A JP S6481253 A JPS6481253 A JP S6481253A JP 62238293 A JP62238293 A JP 62238293A JP 23829387 A JP23829387 A JP 23829387A JP S6481253 A JPS6481253 A JP S6481253A
- Authority
- JP
- Japan
- Prior art keywords
- bonding pads
- package
- mutual connection
- bonding
- internal mutual
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/494—Connecting portions
- H01L2224/4943—Connecting portions the connecting portions being staggered
- H01L2224/49433—Connecting portions the connecting portions being staggered outside the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Abstract
PURPOSE:To shorten a necessary period for development of a product and to reduce a cost therefor by a method wherein a bonding pad for internal mutual connection use and its pattern are wired on a package. CONSTITUTION:Bonding pads 5 for external terminal extraction use, bonding pads 71, 72, 73,... for internal mutual connection use and patterns 8 to mutually connect rows of the bonding pads 71, 72, 73 for specific internal mutual connection use are provided on a semiconductor package 1. On the other hand, bonding pads 3 for external terminal extraction use and bonding pads 4 for internal mutual connection use are provided at a semiconductor chip 2 on the package 1. The bonding pads 3 and 5 are connected by using bonding wires 6. It can be selected flexibly during a posterior process that an arbitrary pad out of the bonding pads 4 is to be connected to one out of the bonding pads 71, 72, 73,... 7n.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62238293A JPS6481253A (en) | 1987-09-22 | 1987-09-22 | Package of semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62238293A JPS6481253A (en) | 1987-09-22 | 1987-09-22 | Package of semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS6481253A true JPS6481253A (en) | 1989-03-27 |
Family
ID=17028036
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62238293A Pending JPS6481253A (en) | 1987-09-22 | 1987-09-22 | Package of semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6481253A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974053A (en) * | 1988-10-06 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for multiple packaging configurations |
US4999700A (en) * | 1989-04-20 | 1991-03-12 | Honeywell Inc. | Package to board variable pitch tab |
US5473196A (en) * | 1993-02-02 | 1995-12-05 | Matra Marconi Space France | Semiconductor memory component comprising stacked memory modules |
US6288941B1 (en) * | 1989-08-18 | 2001-09-11 | Hitachi, Ltd. | Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5748860A (en) * | 1980-09-08 | 1982-03-20 | Canon Inc | Picture synthesizer |
JPS58188142A (en) * | 1982-04-28 | 1983-11-02 | Hitachi Ltd | Ceramic substrate |
-
1987
- 1987-09-22 JP JP62238293A patent/JPS6481253A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5748860A (en) * | 1980-09-08 | 1982-03-20 | Canon Inc | Picture synthesizer |
JPS58188142A (en) * | 1982-04-28 | 1983-11-02 | Hitachi Ltd | Ceramic substrate |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4974053A (en) * | 1988-10-06 | 1990-11-27 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device for multiple packaging configurations |
US4999700A (en) * | 1989-04-20 | 1991-03-12 | Honeywell Inc. | Package to board variable pitch tab |
US6288941B1 (en) * | 1989-08-18 | 2001-09-11 | Hitachi, Ltd. | Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks |
US5473196A (en) * | 1993-02-02 | 1995-12-05 | Matra Marconi Space France | Semiconductor memory component comprising stacked memory modules |
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