JPS5745263A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS5745263A
JPS5745263A JP10235681A JP10235681A JPS5745263A JP S5745263 A JPS5745263 A JP S5745263A JP 10235681 A JP10235681 A JP 10235681A JP 10235681 A JP10235681 A JP 10235681A JP S5745263 A JPS5745263 A JP S5745263A
Authority
JP
Japan
Prior art keywords
base
leads
package
metallization
brazed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10235681A
Other languages
Japanese (ja)
Inventor
Esu Fuii Uiriamu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US16545780A external-priority
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of JPS5745263A publication Critical patent/JPS5745263A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H01L23/057—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body the leads being parallel to the base
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Abstract

A semiconductor package 10 has a braze pad region 22 formed near its periphery and a metallization pattern 18 formed on the base 12 for connecting the leads 24 of the lead frame 20 (which is brazed to the base 12) to the semiconductor die 16 which is mounted on the base by bonding means 28. The package 10 has a pressed ceramic base, and the metallization 18 is screen-printed onto the base so that criteria for automatic wire bonding are met. To aid frame alignment an interconnecting member 26 may be employed that is removed from between the leads 24 of frame 20 after the leads 24 have been brazed to the ceramic base 12. A ceramic base having screen-printed metallization thereon may form a leadless chip carrier. <IMAGE>
JP10235681A 1980-07-02 1981-07-02 Package for semiconductor device Pending JPS5745263A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US16545780A 1980-07-02 1980-07-02

Publications (1)

Publication Number Publication Date
JPS5745263A true JPS5745263A (en) 1982-03-15

Family

ID=22598970

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10235681A Pending JPS5745263A (en) 1980-07-02 1981-07-02 Package for semiconductor device

Country Status (6)

Country Link
JP (1) JPS5745263A (en)
DE (1) DE3123844A1 (en)
FR (1) FR2486307A1 (en)
GB (1) GB2079534A (en)
IT (1) IT8167917D0 (en)
NL (1) NL8102871A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263455A (en) * 1985-09-13 1987-03-20 Hitachi Cable Ltd Manufacture of lead frame
JPS6422043U (en) * 1987-07-30 1989-02-03

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3380082D1 (en) * 1982-10-21 1989-07-20 Abbott Lab A method of establishing electrical connections at a semiconductor device
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
US4987475A (en) * 1988-02-29 1991-01-22 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
EP0357759A1 (en) * 1988-02-29 1990-03-14 Digital Equipment Corporation Alignment of leads for ceramic integrated circuit packages
FR2750798B1 (en) * 1996-07-02 1998-11-06 Sgs Thomson Microelectronics LOW COST BOX FOR INTEGRATED CIRCUITS MADE IN SMALL QUANTITY

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CH526203A (en) * 1968-11-06 1972-07-31 Olivetti & Co Spa Method of assembling one or more electronic circuits integrated in a container
US3550766A (en) * 1969-03-03 1970-12-29 David Nixen Flat electronic package assembly
GB1258870A (en) * 1969-09-29 1971-12-30
US3760090A (en) * 1971-08-19 1973-09-18 Globe Union Inc Electronic circuit package and method for making same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6263455A (en) * 1985-09-13 1987-03-20 Hitachi Cable Ltd Manufacture of lead frame
JPS6422043U (en) * 1987-07-30 1989-02-03

Also Published As

Publication number Publication date
NL8102871A (en) 1982-02-01
FR2486307A1 (en) 1982-01-08
DE3123844A1 (en) 1982-04-08
IT8167917D0 (en) 1981-07-01
GB2079534A (en) 1982-01-20

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