JPS6433938A - Semiconductor memory circuit device - Google Patents

Semiconductor memory circuit device

Info

Publication number
JPS6433938A
JPS6433938A JP62190831A JP19083187A JPS6433938A JP S6433938 A JPS6433938 A JP S6433938A JP 62190831 A JP62190831 A JP 62190831A JP 19083187 A JP19083187 A JP 19083187A JP S6433938 A JPS6433938 A JP S6433938A
Authority
JP
Japan
Prior art keywords
specified
pads
terminals
bonding wire
container
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62190831A
Other languages
Japanese (ja)
Inventor
Shigemitsu Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62190831A priority Critical patent/JPS6433938A/en
Publication of JPS6433938A publication Critical patent/JPS6433938A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Abstract

PURPOSE:To avoid the re-design of the layout of pads and to decrease the number of elements on a semiconductor chip, by connecting a piece of bonding wire by way of the unused terminal of a container. CONSTITUTION:A plurality of terminals 11 are provided in a container 1. A plurality of pads 31, which are connected to inner circuits, are provided in a semiconductor chip 3. The semiconductor chip 3 is mounted and enclosed at a specified position in said container 1. The pads of a plurality of the pads 31 other than the specified pad 31a are connected to the corresponding terminals 11 with a plurality of bonding wires 4. Said specified pad 31a is connected to the specified terminal of a plurality of the terminals 11 by way of the unused terminal 11a, to which the first bonding wire 4 is not connected, among a plurality of the terminals 11 with a second bonding wire 4a. As the second bonding wire 4a, e.g., a delay line, which has a specified length and a specified delay time, is used.
JP62190831A 1987-07-29 1987-07-29 Semiconductor memory circuit device Pending JPS6433938A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62190831A JPS6433938A (en) 1987-07-29 1987-07-29 Semiconductor memory circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62190831A JPS6433938A (en) 1987-07-29 1987-07-29 Semiconductor memory circuit device

Publications (1)

Publication Number Publication Date
JPS6433938A true JPS6433938A (en) 1989-02-03

Family

ID=16264490

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62190831A Pending JPS6433938A (en) 1987-07-29 1987-07-29 Semiconductor memory circuit device

Country Status (1)

Country Link
JP (1) JPS6433938A (en)

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