JPS6477169A - Manufacture of mos transistor - Google Patents

Manufacture of mos transistor

Info

Publication number
JPS6477169A
JPS6477169A JP23247687A JP23247687A JPS6477169A JP S6477169 A JPS6477169 A JP S6477169A JP 23247687 A JP23247687 A JP 23247687A JP 23247687 A JP23247687 A JP 23247687A JP S6477169 A JPS6477169 A JP S6477169A
Authority
JP
Japan
Prior art keywords
gate electrode
accomplished
etching
contact window
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP23247687A
Other languages
Japanese (ja)
Other versions
JP2583243B2 (en
Inventor
Yasuhisa Sato
Tsutomu Saito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP62232476A priority Critical patent/JP2583243B2/en
Publication of JPS6477169A publication Critical patent/JPS6477169A/en
Application granted granted Critical
Publication of JP2583243B2 publication Critical patent/JP2583243B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To protect junction silicon in source.drain regions from breakdown attributable to over-etching by a method wherein a PSG etching process is accomplished, a thermal oxidizing process is accomplished for the surface of a silicon substrate, and then Si3N4 is subjected to etching. CONSTITUTION:An Si3N4 film 24 is formed on a gate electrode 23 and covers the entire surface. Ion implantation is accomplished, with the gate electrode 23 and the Si3N4 film 24 thereon serving as a mask, for the formation of a n<+>-type source region 25 and n<+>-type drain region 26. PSG is deposited on the entire surface by CVD for the formation of an interlayer insulating film 27, contact holes 28 are provided for the source and drain regions 25 and 26, and a contact window 29 is provided for the gate electrode 23. Dry oxidation is accomplished whereby an oxide film 30 is formed on the contact window surfaces in the source and drain regions 25 and 26. The Si3N4 film 24 is removed by RIE from the contact window 28 on the gate electrode 23 for the exposure of the gate electrode 23. The entire surface is exposed to etching for the removal of SiO2 from a silicon substrate contact window portion 27 for the exposure of the substrate. Finally, aluminum is removed by spattering in an RIE process for the construction of an aluminum wiring 31.
JP62232476A 1987-09-18 1987-09-18 Method for manufacturing MOS transistor Expired - Lifetime JP2583243B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62232476A JP2583243B2 (en) 1987-09-18 1987-09-18 Method for manufacturing MOS transistor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62232476A JP2583243B2 (en) 1987-09-18 1987-09-18 Method for manufacturing MOS transistor

Publications (2)

Publication Number Publication Date
JPS6477169A true JPS6477169A (en) 1989-03-23
JP2583243B2 JP2583243B2 (en) 1997-02-19

Family

ID=16939899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62232476A Expired - Lifetime JP2583243B2 (en) 1987-09-18 1987-09-18 Method for manufacturing MOS transistor

Country Status (1)

Country Link
JP (1) JP2583243B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615050B1 (en) * 1992-03-05 2003-09-02 Qualcomm Incorporated Apparatus and method for reducing message collision between mobile stations simultaneously accessing a base station in a CDMA cellular communication system

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687366A (en) * 1979-12-17 1981-07-15 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5687366A (en) * 1979-12-17 1981-07-15 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6615050B1 (en) * 1992-03-05 2003-09-02 Qualcomm Incorporated Apparatus and method for reducing message collision between mobile stations simultaneously accessing a base station in a CDMA cellular communication system

Also Published As

Publication number Publication date
JP2583243B2 (en) 1997-02-19

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