KR930003274B1 - Manufacturing method of mosfet - Google Patents
Manufacturing method of mosfet Download PDFInfo
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- KR930003274B1 KR930003274B1 KR1019900014485A KR900014485A KR930003274B1 KR 930003274 B1 KR930003274 B1 KR 930003274B1 KR 1019900014485 A KR1019900014485 A KR 1019900014485A KR 900014485 A KR900014485 A KR 900014485A KR 930003274 B1 KR930003274 B1 KR 930003274B1
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- South Korea
- Prior art keywords
- gate
- film
- insulating film
- oxide film
- etching
- Prior art date
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- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims abstract description 14
- 238000000034 method Methods 0.000 claims abstract description 9
- 238000005530 etching Methods 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 5
- 238000001312 dry etching Methods 0.000 claims abstract description 4
- 230000005669 field effect Effects 0.000 claims abstract description 4
- 239000002184 metal Substances 0.000 claims abstract description 4
- 229910052751 metal Inorganic materials 0.000 claims abstract description 4
- 230000001590 oxidative effect Effects 0.000 claims abstract description 3
- 238000010438 heat treatment Methods 0.000 claims description 3
- 150000002500 ions Chemical class 0.000 claims 3
- 150000004767 nitrides Chemical class 0.000 claims 2
- 238000000059 patterning Methods 0.000 abstract description 2
- 238000000151 deposition Methods 0.000 abstract 1
- 238000010030 laminating Methods 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 description 4
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 101100202882 Homo sapiens SELENOO gene Proteins 0.000 description 1
- 102100022022 Protein adenylyltransferase SelO, mitochondrial Human genes 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 235000019633 pungent taste Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
- 238000009279 wet oxidation reaction Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
제1도는 종래의 공정단면도.1 is a conventional cross-sectional view of the process.
제2도는 본 발명의 공정단면도.2 is a cross-sectional view of the process of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : P형기판 2 : 필드산화막1: P-type substrate 2: Field oxide film
3 : 게이트절연막 4 : 게이트폴리실리콘막3: gate insulating film 4: gate polysilicon film
5 : 게이트적층절연막 6 : 산화막5 gate laminated insulating film 6 oxide film
7 : 절연막 8 : 금속전극7 insulating film 8 metal electrode
본 발명은 절연게이트형 전계효과 트랜지스터의 제조방법에 관한 것으로, 특히 집적도가 높아지면서 발생하는 핫 캐리어 주입(Hot Carrier Injection)을 감소시키고 게이트 패턴 싸이즈(Gate Pattern SiZe)를 조절하여 고집적화에 적당하도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing an insulated gate field effect transistor. In particular, the present invention relates to reducing hot carrier injection and increasing gate pattern siZe so as to be suitable for high integration. will be.
종래의 게이트 드레인 중첩소자의 제조공정(즉 GOLD공정)을 첨부된 제1(a)도 내지 (d)를 참조하여 상술하면 다음과 같다.The manufacturing process (ie, GOLD process) of the conventional gate drain overlapping element will now be described with reference to the attached first (a) to (d) as follows.
먼저(A)와 같이 기판(9) 위에 게이트 산화막(10)을 형성하고 1차 폴리실리콘(11)을 약 500Å 두께로 증착한 다음 공기중에서 큐어링(Curing)하여 자연산화막(12)을 약 5-10Å 두께로 성장시킨다.First, as shown in (A), the
그리고나서 2차 게이트폴리실리콘(11a) 및 산화막(13)을 증착한 후(B)와 같이 2차 게이트폴리실리콘(11a)을 에치한 다음 n-이온주입을 실시한다.Then, after the secondary gate polysilicon 11a and the
이어(C)와 같이 산화막을 증착하고 이를 건식식각하여 측벽산화막(14)을 형성하여 이 측벽스페이서 외부의 폴리실리콘은 이방성 건식식각법에 의해 제거한다.Subsequently, an oxide film is deposited and dry etched to form a sidewall oxide film 14 as in (C), and polysilicon outside the sidewall spacer is removed by anisotropic dry etching.
마직막으로(D)와 같이 n+이온주입후 습식산화에 의해 SELOCS(Selective Oxide Coating of Silicon Gate)층 (15)을 형성하므로써 게이트와 드레인의 중첩간격을 조절하게 된다.Finally, the overlapping gap between the gate and the drain is controlled by forming SELOCS (Selective Oxide Coating of Silicon Gate) layer 15 by wet oxidation after n + ion implantation as in (D).
그러나 상기 종래기술은 다층게이트 구조와 중첩간격을 조절하기 위하여 SELO CS공정등이 추가되므로 공정이 복잡해지고 따라서 생산율이 저하되며 게이트 커패시턴스가 증가하게 되는 단점이 있었다.However, since the SELO CS process is added to control the multi-layered gate structure and the overlapping gap, the conventional technology has a disadvantage in that the process becomes complicated and thus the yield decreases and the gate capacitance increases.
본 발명은 상기 단점을 제거키 위한 수단으로서 게이트 패턴 싸이즈가 양단 측벽산화막 두께의 여유를 갖도록 하고 게이트와 드레인간의 중첩간격을 조절하는 것을 포함한다.The present invention includes controlling the overlapping gap between the gate and the drain to allow the gate pattern size to have a margin of both sidewall oxide film thickness as a means for eliminating the above disadvantage.
이를 첨부된 제2(a)도 내지 (e)를 참조하여 설명하면 다음과 같다.This will be described with reference to the attached second (a) to (e) as follows.
먼저(A)와 같이 P형기판(1) 위에 필드산화막(2) 형성 후 게이트절연막(3), 게이트폴리실리콘막(4), 게이트적층절연막(무기 혹은 유기계의 산화막)(5)을 차례로 형성한다.First, as shown in (A), after forming the field oxide film 2 on the P-type substrate 1, the gate insulating film 3, the gate polysilicon film 4, and the gate stacked insulating film (inorganic or organic oxide film) 5 are sequentially formed. do.
그리고 (B)와 같이 등방성이온 건식식각법으로 폴리실리콘막(4)의 일부까지를 식각하여 게이트를 패터닝(Patterning)한후 LDD(Lightly Doped Drain) 구조일 경우 저농도의 쉘로우(Shallow)접합형성을 위한 n-이온주입을 실시한다.As shown in (B), the gate is patterned by etching part of the polysilicon layer 4 by isotropic dry etching, and then in the case of LDD (Lightly Doped Drain) structure, a low concentration shallow junction is formed. n - ion implantation is carried out.
이어(C)와 같이 산화성 분위기하에서 열처리 하므로써 게이트 폴리실리콘의 게이트 외측 및 측벽에 산화막(6)이 형성되도록 한다.Then, the oxide film 6 is formed on the outer sidewall and the sidewall of the gate polysilicon by performing heat treatment in an oxidizing atmosphere as shown in (C).
그리고 나서(D)와 같이 게이트적층절연막(5)의 폭만큼 블랭키트식각(Blanket Etch)을 한후 게이트적층절연막(5)을 제거하거나 또는 식각하지 않은 상태로 깊은 접합(Deep Junction) 형성을 위한 n+이온주입을 하고 열처리하여 소오스/드레인을 형성한다.Then, as in (D), a blank kit etching is performed by the width of the gate stacked
이어(E)와 같이 절연막(7)을 증착한 다음 접촉장(Contact Window)을 열고 금속전극(8)을 형성한다.Then, as in E, an insulating film 7 is deposited, and then a contact window is opened to form a metal electrode 8.
상기 공정중 드레인과 게이트의 중첩간격을 제2(c)도에서의 측벽산화조건을 변화시키므로써 측벽산화량을 조절하여 조정할 수 있으며 드레인과 중첩되는 게이트 폴리실리콘막(4) 부위의 형태는 측벽산화를 행할때 형성되는 산화막(6)의 모양에 의해 형성된다.The overlapping interval between the drain and the gate during the process can be adjusted by changing the sidewall oxidation condition in FIG. 2 (c), and the shape of the gate polysilicon film 4 portion overlapping with the drain has a sidewall. It is formed by the shape of the oxide film 6 formed when oxidation is performed.
이상과 같이 본 발명에 의하면 게이트 패턴싸이즈가 양단의 기존의 측벽산화막 두께의 여유를 포함하므로써 서브 미크론 패터닝(Sub micron patterning)에 있어서, 정밀도를 높일 수 있으며 동시에 게이트와 드레인의 중첩간격을 조절하여 핫 전자 주입에 대한 신뢰성을 향상시킬 수 있는 효과가 있다.As described above, according to the present invention, the gate pattern size includes a margin of the thickness of the existing sidewall oxide film at both ends, so that in the sub micron patterning, the precision can be increased, and at the same time, the overlapping gap between the gate and the drain is adjusted to provide hotness. There is an effect that can improve the reliability for electron injection.
Claims (3)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900014485A KR930003274B1 (en) | 1990-09-13 | 1990-09-13 | Manufacturing method of mosfet |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019900014485A KR930003274B1 (en) | 1990-09-13 | 1990-09-13 | Manufacturing method of mosfet |
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| Publication Number | Publication Date |
|---|---|
| KR920007098A KR920007098A (en) | 1992-04-28 |
| KR930003274B1 true KR930003274B1 (en) | 1993-04-24 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019900014485A KR930003274B1 (en) | 1990-09-13 | 1990-09-13 | Manufacturing method of mosfet |
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| KR (1) | KR930003274B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140031759A (en) * | 2012-09-05 | 2014-03-13 | 삼성전자주식회사 | Nitride semiconductor device and method for fabricating the same |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100732272B1 (en) * | 2006-01-26 | 2007-06-25 | 주식회사 하이닉스반도체 | Method for fabricating semiconductor device |
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1990
- 1990-09-13 KR KR1019900014485A patent/KR930003274B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20140031759A (en) * | 2012-09-05 | 2014-03-13 | 삼성전자주식회사 | Nitride semiconductor device and method for fabricating the same |
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| Publication number | Publication date |
|---|---|
| KR920007098A (en) | 1992-04-28 |
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