KR100206920B1 - Method of manufacturing semiconductor device - Google Patents
Method of manufacturing semiconductor device Download PDFInfo
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- KR100206920B1 KR100206920B1 KR1019960028943A KR19960028943A KR100206920B1 KR 100206920 B1 KR100206920 B1 KR 100206920B1 KR 1019960028943 A KR1019960028943 A KR 1019960028943A KR 19960028943 A KR19960028943 A KR 19960028943A KR 100206920 B1 KR100206920 B1 KR 100206920B1
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- oxide film
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- ldd
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 239000004065 semiconductor Substances 0.000 title claims abstract description 11
- 238000000034 method Methods 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims abstract description 9
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000010438 heat treatment Methods 0.000 claims abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 14
- 238000001039 wet etching Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 claims 2
- 230000000593 degrading effect Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 26
- 230000005669 field effect Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000151 deposition Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 238000002955 isolation Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
Abstract
본 발명은, 게이트전극과 소오스/드레인영역 사이의 절연막을 양질의 열산화막으로 형성함으로써, 상기 드레인영역 부근에서 발생되는 하트 캐리어가 상기 열산화막에 트랩되는 것을 방지하여, 반도체소자의 특성이 저하되는 것을 방지하는데 적당하도록 한 반도체소자 제조방법에 관한 것으로, 기판의 소자형성영역 위에 게이트산화막 및 게이트전극을 형성하는 단계와; LDD영역을 형성하기 위한 이온주입 단계와; LDD측벽을 형성하는 단계와; 고농도 소오스/드레인영역을 형성하기 위한 이온주입 단계와; 상기 LDD측벽을 식각하는 단계와; 상기 이온주입영역의 후확산(Drive-in) 및 열산화막을 형성을 동시에 달성할 수 있는 열처리 단계를 포함하여 이루어지는 것을 요지로 한다.The present invention forms an insulating film between the gate electrode and the source / drain regions with a high quality thermal oxide film, thereby preventing the heart carrier generated near the drain region from being trapped by the thermal oxide film, thereby degrading the characteristics of the semiconductor device. A method of fabricating a semiconductor device, the method comprising: forming a gate oxide film and a gate electrode on an element formation region of a substrate; An ion implantation step for forming an LDD region; Forming an LDD side wall; An ion implantation step for forming a high concentration source / drain region; Etching the LDD side wall; The present invention includes a heat treatment step of simultaneously forming a drive-in and a thermal oxide film of the ion implantation region.
Description
제1a도 내지 e도는 종래 기술에 따른 LDD구조 MOS형 전계효과 트랜지스터의 제조방법을 도시한 공정수순도.1A to 1E are process flowcharts showing a method for manufacturing an LDD structure MOS field effect transistor according to the prior art.
제2a도 내지 f도는 본 발명에 따른 LDD구조 MOS형 전계효과 트랜지스터의 제조방법을 도시한 공정수순도.2A to 2F are process flowcharts showing a method for manufacturing an LDD structure MOS field effect transistor according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
21 : 기판 22 : 게이트산화막21 substrate 22 gate oxide film
23 : 게이트전극 24 : LDD영역23: gate electrode 24: LDD region
25 : 측벽스페이서 26 : 고농도 소오스/드레인영역25: sidewall spacer 26: high concentration source / drain region
27 : 열산화막27: thermal oxide film
본 발명은 반도체소자 제조방법에 관한 것으로, 특히 하트 캐리어(Hot Carrier)에 의한 특성 저하를 개선하는데 적당한 반도체소자 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for improving the deterioration of characteristics caused by a hot carrier.
반도체소자 드레인영역을 형성함에 있어서, 채널과 접속되는 영역이 저농도영역으로 형성되는 LDD(Lightly Doped Drain)구조는, 반도체소자가 미세화됨에 따라 발생하는 쇼트채널효과 등을 방지하기 위한 것으로, 특히 드레인영역의 전계를 분산시킴으로써 하트캐리어 효과를 방지하기 위한 것이다.In forming a semiconductor device drain region, an LDD (Lightly Doped Drain) structure in which a region connected to a channel is formed as a low concentration region is for preventing a short channel effect caused by miniaturization of a semiconductor device, in particular, a drain region. This is to prevent the heart carrier effect by dispersing the electric field of.
이하, 첨부된 제1도의 공정수순도를 참조하여, 종래 기술에 따른 LDD구조 MOS형 전계효과 트랜지스터의 제조방법에 대해서 상세히 설명하면 다음과 같다.Hereinafter, a method of manufacturing an LDD structure MOS field effect transistor according to the prior art will be described in detail with reference to the process flowchart of FIG. 1.
제1a도에 도시된 바와 같이, 필드산화막(미도시)에 의하여 소자 형성영역과 소자분리영역이 한정된 기판(11)의 상기 소자형성영역에, 한계전압(VT)를 조절하기 위한 이온을 주입한 후, 게이트산환막(12)을 형성하고, 다결정실리콘(13)을 증착한 후, 포토리소그래피 공정으로 그를 패터닝하여 게이트전극(13)을 완성한다.As shown in FIG. 1A, ions are injected into the device formation region of the substrate 11 where the device formation region and the device isolation region are defined by a field oxide film (not shown) to control the limit voltage V T. Thereafter, the gate conversion film 12 is formed, the polysilicon 13 is deposited, and then patterned by the photolithography process to complete the gate electrode 13.
이후, 제1b도에 도시된 바와 같이, 상기 게이트전극(13)을 마스크로 하는 저농도 이온주입공정을 실시한 후, 제1c도에 도시된 바와 같이, 상기 결과물의 전면에 산화막(15a)을 화학기상성장법(CVD)으로 증착한다. 미설명 부호 14a는 기판(11)에 주입된 저농도 이온을 나타낸다.Subsequently, as shown in FIG. 1B, after performing a low concentration ion implantation process using the gate electrode 13 as a mask, as shown in FIG. 1C, the oxide film 15a is chemically deposited on the entire surface of the resultant product. Deposition by growth method (CVD). Reference numeral 14a denotes low concentration ions implanted into the substrate 11.
이어서, 제1d도에 도시된 바와 같이, 이방성 건식각법으로 상기 산화막(15a)을 시각하여 LDD측벽스페이서(15)를 형성한 후, 고농도 이온을 주입한다. 미설명 부호 16a는 기판(11)에 주입된 고농도 이온을 나타낸다.Subsequently, as shown in FIG. 1D, the LDD side wall spacer 15 is formed by viewing the oxide film 15a by anisotropic dry etching, and then high concentration ions are implanted. Reference numeral 16a denotes a high concentration of ions implanted into the substrate 11.
마지막으로, 제1e도에 도시된 바와 같이, 기판(11)에 주입된 이온을 재분포 및 활성화시키기 위한 열처리 공정으로, LDD영역(14)과 고농도의 소오스/드레인영역(16)에 대한 공정을 완성한다. 이후, 계속되는 공정에서는 상기 결과물 위에 층간절연산화막을 증착한 후, 그 층간절연산화막을 선택적으로 식각함으로써 콘택홀을 형성하고, 그 위에 금속을 증착한 후, 금속박막을 패터닝하여 금속전극을 형성하는 배선공정을 수행한다.Finally, as shown in FIG. 1E, as a heat treatment process for redistributing and activating ions implanted into the substrate 11, a process for the LDD region 14 and the high concentration source / drain region 16 is performed. Complete Subsequently, in the subsequent process, after depositing the interlayer dielectric oxide film on the resultant, the contact hole is formed by selectively etching the interlayer dielectric oxide film, the metal is deposited thereon, and then the metal thin film is patterned to form a metal electrode. Perform the process.
이와 같은 공정을 통해 형성된 LDD구조 MOS형 전계효과 트랜지스터는, 채널영역과 고농도 드레인영역 사이에 형성된 LDD영역으로 인하여, 그 드레인영역의 전계가 분산됨으로써 통상적인 MOS형 전계효과 트랜지스터에 비해서 하트 캐리어 효과가 개선되는 효과가 있다.The LDD structure MOS field effect transistor formed through such a process has a heart carrier effect compared to the conventional MOS field effect transistor because the field of the drain region is dispersed due to the LDD region formed between the channel region and the high concentration drain region. There is an improvement effect.
그러나 상기 종래 기술은, LDD를 형성하기 위한 측벽이 질(Quality)이 낮은 산화막 등으로 형성되었음에도 불구하고, 그 산화막이 게이트전극과 드레인영역을 절연하기 위한 절연층으로 사용됨으로써, 드레인영역 부근에서 발생되는 하트 캐리어가 상기 측벽에 트랩(Trap)되는 문제점을 야기시켰다. 즉, 상기 측벽이 하트 캐리어를 트랩함으로써, LDD영역에 캐리어 공핍(Carrier Depletion)이 생겨, LDD영역의 저항 증가로 소자의 특성이 저하되는 문제점이 발생하였다.However, in the above conventional technique, although the side wall for forming the LDD is formed of an oxide film of low quality or the like, the oxide film is used as an insulating layer for insulating the gate electrode and the drain region, thereby generating near the drain region. The resulting heart carrier trapped the sidewalls. That is, since the sidewall traps the heart carrier, carrier depletion occurs in the LDD region, resulting in a problem of deterioration of device characteristics due to an increase in resistance of the LDD region.
이에 본 발명은 상기와 같은 문제점을 해결하기 위하여 창안한 것으로, 게이트전극과 소오스/드레인영역 사이의 절연막을 질이 우수한 절연막으로 형성함으로써, 상기 드레인영역 부근에서 발생되는 하트 캐리어가 상기 절연막에 트랩되는 것을 방지하여, 반도체소자의 특성이 저하되는 것을 방지하는데 적당하도록 한 반도체소자 제조방법을 제공함에 목적이 있다.Accordingly, the present invention has been made to solve the above problems, and by forming an insulating film between the gate electrode and the source / drain regions as a good insulating film, a heart carrier generated near the drain region is trapped in the insulating film. It is an object of the present invention to provide a method for manufacturing a semiconductor device, which is suitable for preventing the degradation of the characteristics of the semiconductor device.
상기 목적을 달성하기 위한 본 발명은 기판의 소자형성영역 위에 게이트 산화막 및 게이트전극을 형성하는 단계와; LDD영역을 형성하기 위한 이온주입 단계와; LDD측벽을 형성하는 단계와; 고농도 소오스/드레인영역을 형성하기 위한 이온주입 단계와; 상기 LDD측벽을 식각하는 단계와; 상기 공정을 위해, 기판에 주입된 이온을 후확산(Drive-in)시키는 단계 및 양질의 절연막을 상기 결과물의 전면에 형성하는 단계를 포함하여 이루어지는 것을 특징으로 한다.The present invention for achieving the above object comprises the steps of forming a gate oxide film and a gate electrode on the element formation region of the substrate; An ion implantation step for forming an LDD region; Forming an LDD side wall; An ion implantation step for forming a high concentration source / drain region; Etching the LDD side wall; For this process, the method comprises the step of driving the ion implanted into the substrate (Drive-in) and forming a good quality insulating film on the entire surface of the result.
특히, 본 발명은, 상기 양질의 절연막이 열산화막으로 구성하도록 함으로써, 그 열산화막이 상기 후확산(Drive-in)을 위한 열처리 공정을 통해 형성되도록 하는 것을 특징으로 한다.In particular, the present invention is characterized in that the thermal insulating film of the high-quality insulating film to be formed through a heat treatment process for the drive-in.
이하, 첨부된 도면 제2도의 공정 수순도를 참조하여 본 발명의 바람직한 실시예에 대해서 상세히 설명한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the process flowchart of FIG. 2.
제2a도에 도시된 바와 같이, 필드산화막(미도시)에 의하여 소자형성영역과 소자분리영역과 소자분리영역이 한정된 기판(21)의 상기 소자형성영역에, 한계전압(VT)를 조절하기 위한 이온을 주입한 후, 게이트산화막(22)을 형성하고, 다결정실리콘(23)을 증착한 후, 포토리소그래피 공정으로 그를 패터닝하여 게이트전극(23)을 완성한다. 이때 상기 공정은 기판(21)에 웰을 형성한 후, 그 웰에 상기 공정을 수행할 수도 있다.As shown in FIG. 2A, the threshold voltage V T is controlled in the device formation region of the substrate 21 in which the device formation region, the device isolation region, and the device isolation region are defined by a field oxide film (not shown). After implanting the ions, the gate oxide film 22 is formed, the polysilicon 23 is deposited, and then patterned by the photolithography process to complete the gate electrode 23. In this case, the well may be formed on the substrate 21, and then the process may be performed on the well.
이후, 제2b도에 도시된 바와 같이, 상기 게이트전극(23)을 마스크로 하는 저농도 이온주입공정을 실시한 후, 제1c도에 도시된 바와 같이, 상기 결과물의 전면에 산화막(25a)을 화학기상성장법(CVD)으로 증착한다. 여기서 상기 제2b도에 도시된 점선(24a)은 기판(21)에 주입된 이온이 저농도임을 나타낸다.Subsequently, as shown in FIG. 2B, after performing a low concentration ion implantation process using the gate electrode 23 as a mask, as shown in FIG. 1C, the oxide film 25a is chemically deposited on the entire surface of the resultant product. Deposition by growth method (CVD). Here, the dotted line 24a shown in FIG. 2B indicates that the ions implanted into the substrate 21 are low in concentration.
이어서, 제2d도에 도시된 바와 같이, 이방성 건식각법으로 상기 산화막(25a)을 식각하여 LDD측벽스페이서(25)을 형성한 후, 고농도 이온을 주입한다. 이때 굵은 일점 쇄선(26a)는 기판(21)에 주입된 이온이 고농도임을 나타낸다.Subsequently, as shown in FIG. 2D, the oxide film 25a is etched by the anisotropic dry etching method to form the LDD side wall spacer 25, and then high concentration ions are implanted. At this time, the thick dashed-dotted line 26a indicates that the ions implanted into the substrate 21 are high in concentration.
그리고, 제2e도에 도시된 바와 같이, 습식각법으로 상기 LDD측벽스페이서(25)를 식각한 후, 제2f도에 도시된 바와 같이, 기판(21)에 주입된 이온을 재분포 및 활성화시킥 위한 열처리(어닐링) 공정을 수행하면서, 상기 게이트전극(23)을 포함한 기판(21)의 전면에 양질의 열산화막(Thermal Oxide)(27)을 형성한다.As shown in FIG. 2E, after the LDD sidewall spacer 25 is etched by wet etching, redistribution and activation of ions implanted into the substrate 21 are performed as shown in FIG. 2F. While performing a heat treatment (annealing) process, a high quality thermal oxide 27 is formed on the entire surface of the substrate 21 including the gate electrode 23.
이후, 계속되는 반도체소자 제조공정은 상기 결과를 위에 층간절연산화막을 증착한 후, 그 층간절연산화막을 선택적으로 식각함으로써 콘택홀을 형성하고, 그 위에 금속을 증착한 후, 금속박막을 패터닝하여 금속전극을 형성하는 배선공정을 수행한다.Subsequently, the subsequent semiconductor device manufacturing process results in depositing an interlayer insulating oxide film on the result, and then forming a contact hole by selectively etching the interlayer insulating oxide film, depositing a metal thereon, and then patterning the metal thin film to form a metal electrode. Perform the wiring process to form a.
이와 같은 제조방법은 기판(21)에 주입된 이온을 후확산(Drive-in)시키기 위한 통상적인 열처리 공정을 통해, 게이트전극을 포함하는 소자의 전면에 양질의 열산화막을 형성함으로써, 그 방법을 통해 형성되는 LDD구조 MOS형 전계효과 트랜지스터가 상기 양질의 열산화막으로 게이트전극과 소오스/드레인영역 사이의 절연막을 구성하게 되어, 드레인영역 부근에서 발생되는 하트 캐리어(Hot Carrier)를 트랩(Trap)하지 않는 효과를 발생시킨다.Such a manufacturing method is achieved by forming a high quality thermal oxide film on the front surface of a device including a gate electrode through a conventional heat treatment process for driving-in ions implanted into the substrate 21. The LDD structure MOS field effect transistor formed through the high-quality thermal oxide film forms an insulating film between the gate electrode and the source / drain regions, and does not trap a hot carrier generated near the drain region. Does not produce effects.
Claims (4)
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