JP2583243B2 - Method for manufacturing MOS transistor - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to a method for forming a contact hole with a MOS transistor, particularly with a gate electrode, for opening a contact window with the gate electrode when the gate electrode surface is covered with a nitride film. In order to prevent the silicon substrate in the source and drain regions from being over-etched when etching the nitride film, an oxide film is formed once on the surface of the silicon substrate in the source and drain regions, and then the nitride film on the gate electrode is formed. By performing the above etching, the oxide film is made to act as an etching stopper.

[Industrial applications]

 The present invention relates to a method for manufacturing a MOS transistor.

[Problems to be solved by conventional technology and invention]

Conventionally, polycrystalline silicon and silicide of various metals (MoSi ₂ , WSi _2, etc.) have been used for the gate electrode of MOS type semiconductor devices. The use of high melting point metals, such as W and Mo, which further reduce the temperature, has been strongly desired.

However, in the case of W or Mo in the later step II (ion implantation), a channeling phenomenon occurs, and ions implanted reach the substrate under the gate, or
A problem not found in silicon gates or polysilicon / silicide (polycide) gates arises, such as being easily oxidized during heat treatment and all of them becoming oxides.

In order to prevent this channeling and oxidation, it is necessary to cover the surface of W or Mo. Conventionally, there is an example using PSG for this cover film. (Extended Abstracts of the 15th Confe
rence on Solid State Devices and Materials, Tokyo, 1
983 Pp217～220, Hitachi) but when the etching for forming the gate electrode is a film of SiO ₂ system, W in a reactive ion etch (RIE)
And Mo's side etch advances, causing undercut. FIG. 2 shows this state. A gate insulating film 2, a W or Mo gate electrode 3 is formed on a silicon substrate 1, an oxide film 4 is formed on the gate electrode 3, and patterned with a resist 5. Then, the gate electrode 3 is undercut (side-etched). When the undercut occurs, the precision is required most in the fine MOS type transistor. The control of the gate length is no longer based solely on the mask, and becomes extremely difficult.

It is known that when Si ₃ N ₄ is deposited on a W or Mo gate electrode material instead of SiO ₂ or PSG, the undercut as described above is eliminated and the dimensional accuracy of the gate length can be improved. (Spring 62, Japan Society of Applied Physics 31 P-P
-8).

However, in this case, there are the following problems. Third
This will be described with reference to the drawings. In FIG. 3A, 11 is a p-type silicon substrate, 12 is a gate oxide (SiO ₂ ), 13 is an n ^{+ -type} diffusion region (source and drain regions), 14 is a W or Mo gate electrode, and 15 is Si ₃ N ₄ film and 16 are PSG interlayer insulating films.
A contact window with the gate electrode 14 and the n ⁺ diffusion region 13 is opened in the interlayer insulating film 16, and on the gate electrode 14
While the Si ₃ N ₄ film 15 serves as a stopper, the silicon substrate 11
Is exposed. Next, RIE (reactive ion etching) is performed on the Si ₃ N ₄ film 15 to open a contact window with the gate electrode 14.
3B, it is difficult to obtain an etching rate between Si ₃ N ₄ and silicon. Therefore, as shown in FIG. 3B, the contact portion of the silicon substrate 11 is over-etched, and the depth of the n ^{+ type} diffusion region 13 is small. In some cases, junction breakdown may occur.

[Means for solving the problem]

According to the present invention, in order to solve the above-mentioned problem, after etching the PSG, the surface of the silicon substrate is thermally oxidized and then the Si ₃ N ₄ is etched. Since SiO ₂ grows much slower on Si ₃ N ₄ than on a silicon substrate, almost no SiO ₂ is formed. Since Si ₃ N ₄ and SiO ₂ have a sufficient etching selectivity, and both SiO ₂ and W or Mo have a sufficient etching selectivity, a contact window can be formed without any problem.

That is, the present invention forms an oxide gate insulating film on a silicon semiconductor substrate, forms a gate electrode on the gate insulating film, forms a nitride insulating film on the gate electrode, and then forms the gate electrode and the substrate. An oxide insulating film is formed on the entire surface,
After patterning the oxide-based insulating film to open the contact window for the gate electrode and the contact film for the silicon semiconductor substrate, the surface of the contact window portion of the opened silicon semiconductor substrate is selectively oxidized to etch the next nitride insulating film. Forming a contact window with the gate electrode in the nitride insulating film on the gate electrode by etching, and removing the surface oxide film at the contact window portion of the silicon semiconductor substrate.
It is in a method for manufacturing a MOS transistor.

〔Example〕

 This will be described with reference to FIG.

Referring to FIG. 1A, a surface of a p-type silicon substrate 21 is thermally oxidized to form a gate oxide film 22 having a thickness of about 200 °. In order to form a gate electrode 23 on the gate oxide film 22, W (or Mo) is deposited to a thickness of about 2000 mm by sputtering, and a Si ₃ N ₄ film 24 is formed thereon to a thickness of about 1000 mm by CVD. Perform patterning. Thereafter, Si ₃ N ₄ is deposited again on the entire surface and reactive ion etching is performed to form a Si ₃ N ₄ film also on the side wall of the gate electrode 23. This is to prevent W from being oxidized by contact with PSG.

Referring to FIG. 1B, the gate electrode 23 and the Si
_{Using the 3} N ₄ film 24 as a mask, an n ^{+ -type} source region 25 and an n ⁺ -type drain region 26 are formed by ion implantation. Then, PSG is deposited on the entire surface to a thickness of about 1.0 μm by CVD to form an interlayer insulating film 27.
Are formed, and contact windows 28 for the source and drain regions 25 and 26 and a contact window 29 for the gate electrode 23 are opened. RIE using a mixed gas of CF ₄ and CHF ₃
Perform in. Since the etching selectivity of Si ₃ N ₄ and silicon with respect to PSG is sufficient, after the etching of PSG is completed,
The Si ₃ N ₄ film 24 remains on the gate electrode 23, while the source
Since the oxide film 22 is extremely thin on the drain regions 25 and 26, it is completely etched to expose the silicon substrate.

Referring to FIG. 1C, now in accordance with the present invention, at 950 ° C.
Dry oxidation in the source / drain regions 25, 26
An oxide film 30 having a thickness of about 500 mm is formed on the surface of the contact window. At this time, Si ₃ N ₄ is hardly oxidized.

Referring to FIG. 1D, the Si ₃ N ₄ film 24 in the contact window 28 on the gate electrode 23 is etched by RIE to form the gate electrode 23.
To expose. This RIE is performed with CF ₄ + O ₂ . At this time,
Since the oxide film 30 has a sufficient etching selectivity with respect to Si ₃ N ₄ , the oxide film 30 remains on the substrate even after the removal of Si ₃ N ₄ .

Referring to FIG. 1E, the entire surface is again etched by RIE using a mixed gas of CF ₄ + CHF ₃ to remove the SiO ₂ in the contact window 27 of the silicon substrate and expose the substrate. At this time, the gate electrode 23 is not etched.

Referring to FIG. 1F, aluminum containing 1% of silicon is deposited to a thickness of 1.0 μm by sputtering and etched by RIE using a mixed gas of BCl ₃ and Cl ₂ to form an aluminum wiring 31.

The following is not shown in the figure, but PSG of 1.0μm pressure by CVD method
Is deposited, and the PSG of the external lead wire bonding pad is opened to form a MOS semiconductor device.

〔The invention's effect〕

According to the method of the present invention, when a W or Mo gate using Si ₃ N ₄ on the gate electrode is used, when etching the interlayer insulating film at the contact portion with the upper aluminum electrode wiring, the source
It is possible to eliminate the possibility that the silicon in the drain region is over-etched to cause a junction breakdown.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a sectional view of a MOS transistor as a main part of a process according to an embodiment of the present invention, FIG. 2 is a sectional view showing a state of etching a W or Mo gate electrode of a conventional example, and FIG. The figure is a cross-sectional view of a conventional example of manufacturing a MOS transistor. DESCRIPTION OF SYMBOLS 1 ... Silicon substrate, 2 ... Gate oxide film, 3 ... W or Mo gate electrode, 4 ... Oxide type film, 5 ... Resist, 11 ... Silicon substrate, 12 ... Gate oxide film, 13 ... ... n ⁺ form diffusion regions, 14 ...... W or Mo gate electrode, 15 ...... Si ₃ n ₄ film, 16 ...... PSG film, 21 ...... silicon substrate, 22 ...... gate oxide film, 23 ...... W (Mo ) gate electrodes, 24 ...... Si ₃ N ₄ film, 25 ...... source region, 26 ...... drain region, 27 ...... PSG interlayer insulating film, 28 and 29 ...... contact window, 30 ...... oxide film, 31 ...... Aluminum wiring.

Claims (1)

(57) [Claims] An oxide gate insulating film is formed on a silicon semiconductor substrate, a gate electrode is formed on the gate insulating film, and a nitride insulating film is formed on the gate electrode. Forming an oxide-based insulating film on the substrate, patterning the oxide-based insulating film and opening a contact window for the gate electrode and a contact window for the silicon semiconductor substrate, and selectively opening the contact window portion of the opened silicon semiconductor substrate to the surface; Oxidize to serve as a stopper for the next nitride insulating film etching, and then open a contact window with the gate electrode in the nitride insulating film on the gate electrode by etching,
And a step of removing a surface oxide film at a contact window portion of the silicon semiconductor substrate.