JPH07142710A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To suppress the oxidation of palycrystal silicon treated with patterning by sequentially removing the second gate insulation film formed an the first insulation film and then the first one so that a gate electrode is patterned an the first and second insulation films. CONSTITUTION:By thermal oxidation, a silicon oxidation film 6 of 16nm is formed as the second gate insulation film, different from the first gate insulation film in film thickness. At that time, a silicon oxidation film is formed on oxide films 4 and 5 as well. Further, through depression CVD method, a polycrystal silicon film 7 is deposited. A resist pattern R2 far patterning the polycrystal silicon film 7 is formed, and the palycrystal silicon film 7 is patterned by CDE. The resist pattern R2 is removed and the silicon oxidation films 4-6 are removed by wet-etching with the use of ammonium fluoride. The polycrystal silicon film is not directly oxidized in the following direct contact formation and gate electrode formation processes.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, which is used for forming a gate electrode having a direct contact using gate insulating films having different film thicknesses.

[0002]

2. Description of the Related Art Conventionally, as a method of forming a semiconductor memory device having a gate electrode having a direct contact formed on a gate insulating film having a different film thickness, the steps shown in FIGS. Are known.

That is, first, as shown in FIG. 3 (a), a silicon oxide 2 as a gate electrode is formed on the surface of a silicon substrate 1 on which a field oxide film 8 and a desired element region are formed, and an upper layer of this is formed. A crystalline silicon film 3 is formed.

Next, as shown in FIG. 3B, a resist pattern R1 is formed by photolithography on the polycrystalline silicon film 3 on the gate insulating film side on one of the element formation regions separated by the field oxide film 8. . Then, the portion of the polycrystalline silicon film 3 which is not covered with the resist R1 is etched by using chemical dry etching (CDE).

Then, as shown in FIG. 3C, the resist pattern R1 is removed. Then, the silicon oxide film 2 on the element forming region where the gate insulating film having a different film thickness is to be formed is removed by wet etching with ammonium fluoride,
Then, thick silicon oxide 6 is formed by thermal oxidation.
At this time, the patterned polycrystalline silicon film 7 is also oxidized. Then, a polycrystalline silicon film 7 is formed on this upper layer.

Next, as shown in FIG. 3D, a resist pattern R2 is formed on a portion of the polycrystalline silicon film 7 and the field oxide film 8 on the thick gate insulating film 6 by photolithography. Then, the polycrystalline silicon film 7 is patterned by CDE using the resist pattern R2 as a mask.

Thereafter, as shown in FIG. 3E, the oxide film formed on the previously patterned polycrystalline silicon film 3 is removed by wet etching with ammonium fluoride.

However, when a gate electrode is formed on the gate insulating film having a different film thickness as in the conventional method described above, the etching liquid is exposed to the underlying gate insulating film during the wet etching shown in FIG. 3 (e). However, this causes defective insulation withstand voltage of the insulating film, resulting in a decrease in yield.

[0009]

As described above, according to the conventional method, the patterned polycrystalline silicon film is oxidized when the gate insulating films having different thicknesses are formed. Then, by removing the oxide film by wet etching with ammonium fluoride, there is a problem that the underlying gate insulating film is affected and the breakdown voltage of the gate insulating film is deteriorated.

The present invention has been made in view of the above circumstances, and when a gate electrode is formed on two types of gate insulating films having different film thicknesses, the breakdown voltage of the gate insulating film does not occur and reliability is improved. An object of the present invention is to provide a method for manufacturing a semiconductor device having a high gate electrode of a transistor.

[0011]

In order to achieve the above object, the present invention provides an element isolation region and a first element formation region and a second element formation region which are separated by the element isolation region. Forming a first gate insulating film on a semiconductor substrate, depositing a polycrystalline silicon film on the first gate insulating film, and depositing a first insulating film on the polycrystalline silicon film A step of forming a resist pattern on the first insulating film so as to cover the first element formation region and a part of the element isolation region, and the first resist using the patterned resist as a mask By sequentially etching the insulating film and the polycrystalline silicon film, the first insulating film and the polycrystalline silicon are formed on the first gate insulating film and the element isolation region on the first element forming region. Selectively removing the first gate insulating film exposed on the second element forming region, and removing at least the second gate insulating film by thermal oxidation. A step of forming a second gate insulating film having a thickness different from that of the first insulating film on the element forming region, and a part of the second gate insulating film on the second element forming region and the element isolation region A step of selectively forming a polycrystalline silicon film again, and removing the resist,
A step of sequentially removing the second gate insulating film and the first insulating film formed on the first insulating film by wet etching, and patterning a gate electrode on the first and second gate insulating films And a method of forming a semiconductor device.

Preferably, the first gate insulating film and the first isolation layer are selectively left on the first isolation layer and the element isolation region.
And a step of selectively forming a second insulating film on the side surfaces of the insulating film and the end portion of the polycrystalline silicon film.

[0013]

According to the above structure, it is possible to suppress the oxidation of the previously patterned polycrystalline silicon during the thermal oxidation when forming the gate insulating film having a different film thickness. Therefore, the oxidation on the patterned polycrystalline silicon film is suppressed. Since it is possible to prevent the first gate insulating film from being affected by wet etching with ammonium fluoride or the like for removing the film, a highly reliable method for manufacturing a semiconductor device can be provided.

[0014]

Embodiments of the present invention will now be described in detail with reference to the drawings. Example 1 FIGS. 1A to 1G are process sectional views showing a method for manufacturing a semiconductor device according to an example of the present invention.

First, as shown in FIG. 1A, a silicon oxide film 2 as a first gate insulating film is formed on a silicon substrate 1 having a field oxide film 8 formed in a desired element isolation region by thermal oxidation. 13 nm is formed, and then the polycrystalline silicon film 3 is deposited to 50 nm by the low pressure CVD method. Then, the silicon oxide film 4 is deposited to a thickness of 50 nm by the low pressure CVD method.

Next, as shown in FIG. 1B, a resist pattern R1 for patterning the polycrystalline silicon film 3 and the silicon oxide film 4 is formed by photolithography. Then, reactive ion etching (RIE)
Patterning of the silicon oxide film 4 is performed, and then the polycrystalline silicon film 3 is patterned by chemical dry etching (CDE).

Thereafter, as shown in FIG. 1C, the resist pattern R1 is removed, and then a silicon oxide film 5 is deposited to a thickness of 50 nm by a low pressure CVD method. Next, as shown in FIG. 1D, the silicon oxide film 5 is etched by RIE, but at this time, the silicon nitride film 5 is left on the sidewalls of the patterned polycrystalline silicon film 3. Then, for example, annealing is performed in a nitrogen atmosphere to reduce the etching rate of the oxide films 4 and 5 with ammonium fluoride.

The cause of the exudation of the etching solution into the first gate insulating film 2 is that oxygen is taken into the polycrystalline silicon film 3 in the oxidation step when forming the second gate insulating film having a different film thickness. It is considered that this is due to the presence of oxygen. Therefore, as shown in FIG. 1D, the polycrystalline silicon film 3
By covering the oxide films 4 and 5, it is possible to prevent oxygen from entering during oxidation.

Then, as shown in FIG. 1E, the silicon oxide film 2 in the element forming region is removed by wet etching by exposing it to ammonium fluoride for 12 seconds in order to form gate insulating films having different thicknesses. At this time, it is necessary to prevent the patterned oxide films 4 and 5 from exposing the polycrystalline silicon film 3 by wet etching. Then, the silicon oxide film 6 is formed as a second gate insulating film having a thickness different from that of the first gate insulating film by thermal oxidation.
6 nm is formed. At this time, a silicon oxide film is also formed on the oxide films 4 and 5. Then, the polycrystalline silicon film 7 is further deposited by the low pressure CVD method.

Next, as shown in FIG. 1F, a resist pattern R2 for patterning the polycrystalline silicon film 7 is formed by photolithography. Then, the polycrystalline silicon film 7 is patterned by CDE.

Then, as shown in FIG. 1G, the resist pattern R2 is removed, and the silicon oxide films 4, 5 and 6 deposited on the polycrystalline silicon film 3 are removed by wet etching with ammonium fluoride. .

After the polycrystalline silicon film is formed on the gate insulating films having different film thicknesses in this manner, subsequent steps such as a direct contact forming step and a gate electrode forming step are performed.

When a gate insulating film having a different film thickness is formed in the subsequent step formed in this manner, the previously patterned polycrystalline silicon film is not directly oxidized, so that the gate insulating film is wet-etched. Since there is no influence, it is possible to prevent the breakdown voltage of the gate insulating film from being defective, and it is possible to obtain a highly reliable semiconductor device.

Embodiment 2 FIGS. 2A to 2E are process sectional views showing a method of manufacturing a semiconductor device according to another embodiment of the present invention.

First, as shown in FIG. 2A, a silicon oxide film 2 as a gate insulating film having a thickness of 13 nm is formed by thermal oxidation on a silicon substrate 1 having a field oxide film 8 formed in a desired element isolation region. Then, a polycrystalline silicon film 3 is deposited to a thickness of 50 nm by the low pressure CVD method. Then, a silicon oxide film 4 is deposited to a thickness of 150 nm by the low pressure CVD method.

Next, as shown in FIG. 2B, a resist pattern R1 for patterning the polycrystalline silicon film 3 and the silicon oxide film 4 is formed by photolithography. Then, the silicon oxide film 4 is patterned by RIE, and then the polycrystalline silicon film 3 is patterned by CDE.
Pattern.

Then, as shown in FIG. 2C, the silicon oxide film 2 in the regions where the gate insulating films having different thicknesses are formed is removed by wet etching in which ammonium fluoride is exposed for 12 seconds, and the regions are thermally oxidized. Silicon oxide film 6
16 nm is formed. At that time, the patterned oxide film 4 is annealed in a nitrogen atmosphere in order to prevent the polycrystalline silicon film 3 from being exposed by wet etching. Then, a polycrystalline silicon film 7 is deposited to a thickness of 50 nm by the low pressure CVD method.

Thereafter, as shown in FIG. 2D, a resist pattern R2 for patterning the polycrystalline silicon film 7 is formed by photolithography. Then, the polycrystalline silicon film 7 is patterned by CDE.

Then, as shown in FIG. 2E, the resist pattern R2 is removed, and the silicon oxide film 4 deposited on the polycrystalline silicon film 3 is removed by wet etching with ammonium fluoride for 12 seconds.

After the gate insulating films having two kinds of film thickness are formed in this manner, subsequent steps such as a direct contact forming step and a gate electrode forming step are performed. This embodiment is different from the above-mentioned embodiments in that the patterned polycrystalline silicon film 3 is covered with silicon oxide films 4 and 5 deposited by a low pressure CVD method and then the other gate insulating film 6 is used. In contrast to this, in this embodiment, the polycrystalline silicon film 3 deposited on the first gate insulating film is covered with the silicon oxide film 4 deposited by the low pressure CVD method. The oxide film 4 on the sidewall.
Is not covered by. That is, if the pattern edge of the polycrystalline silicon film reaches the field oxide film 8, it is considered that oxygen hardly penetrates from the side wall to the vicinity of the first gate insulating film. Therefore, according to this embodiment, the same effect as that of the above embodiment can be obtained for the first insulating film, and the number of steps can be reduced. In addition, in the second embodiment, it is preferable to form the gate insulating film having a large film thickness before forming the thin gate insulating film having the film thickness. This is because if the steps are performed in this order, the degree of oxidation of the sidewalls of the previously patterned polycrystalline silicon film 3 is reduced and the influence of the first gate insulating film is reduced.

In the above embodiments, the oxide film on the polycrystalline silicon film is described as being deposited by the low pressure CVD method, but it may be an oxide film by the atmospheric pressure CVD method. Also CVD
The method is not limited to the oxide film formed by the method, and a silicon nitride film may be used. However, in this case, CVD is used instead of wet etching as removal after patterning the polycrystalline silicon film.

In the gate electrode forming step, MoS is used.
Although a high melting point metal polycide such as i or TiSi is assumed, another conductive material such as polycrystalline silicon may be used. In addition, various modifications can be made without departing from the scope of the present invention.

[0033]

As described above, according to the present invention, the second gate insulating film is formed after the exposed portion of the patterned polycrystalline silicon film is covered with the insulating film.
Oxidation of the polycrystalline silicon film can be suppressed, influence on the first gate insulating film due to wet etching in a later step can be prevented, and a highly reliable semiconductor device can be obtained.

[Brief description of drawings]

FIG. 1 is a process drawing showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a process drawing showing the manufacturing method of the semiconductor device according to the second embodiment of the present invention.

3A to 3C are process diagrams for explaining a conventional method for manufacturing a semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Silicon substrate 2 ... Silicon oxide film 3 ... Polycrystalline silicon film 4 ... Silicon nitride film 5 ... Silicon nitride film 6 ... Silicon oxide film 7 ... Polycrystalline silicon film 8 ... Field oxide film R1 ... Resist pattern R2 ... Resist pattern

Claims (2)

[Claims] 1. A step of forming a first gate insulating film on a semiconductor substrate provided with an element isolation region and a first element formation region and a second element formation region separated by the element isolation region, A step of depositing a polycrystalline silicon film on the first gate insulating film, and a first step on the polycrystalline silicon film.
A step of depositing an insulating film, a step of forming a resist pattern on the first insulating film so as to cover the first element formation region and a part of the element isolation region, and the patterned resist By sequentially etching the first insulating film and the polycrystalline silicon film with the mask as a mask, the first insulating film is formed on the first gate insulating film and the element isolation region on the first element formation region. A step of selectively leaving the film and the polycrystalline silicon film, a step of removing the resist after that, a step of removing the first gate insulating film exposed on the second element formation region, and a thermal oxidation. A step of forming a second gate insulating film having a film thickness different from that of the first gate insulating film on at least the second element forming region, and on the second gate insulating film on the second element forming region, and element A step of selectively forming a polycrystalline silicon film again on a part of the isolated region; a resist is removed; and a second gate insulating film and the first gate insulating film formed on the first insulating film by wet etching. And a step of patterning a gate electrode on the first and second gate insulating films. 2. A second insulating film is selected on a side surface of an end portion of the first insulating film and the polycrystalline silicon film left selectively on the first gate insulating film and the element isolation region. 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming the same.