JPS6468048A - Asynchronous control system - Google Patents

Asynchronous control system

Info

Publication number
JPS6468048A
JPS6468048A JP62224625A JP22462587A JPS6468048A JP S6468048 A JPS6468048 A JP S6468048A JP 62224625 A JP62224625 A JP 62224625A JP 22462587 A JP22462587 A JP 22462587A JP S6468048 A JPS6468048 A JP S6468048A
Authority
JP
Japan
Prior art keywords
equipment
phased
clock
internal
clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62224625A
Other languages
Japanese (ja)
Inventor
Ikutoshi Igawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62224625A priority Critical patent/JPS6468048A/en
Publication of JPS6468048A publication Critical patent/JPS6468048A/en
Pending legal-status Critical Current

Links

Landscapes

  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To synchronize with a period shorter than that of an internal clock and to execute communication with other equipment at a high speed by making the internal clock multi-phased spuriously, and synchronizing with one of the multi-phased internal clocks. CONSTITUTION:Two internal clocks I5 and III7, for instance, are inverted and antiphase clocks the inverse of -I6 and the inverse of -III8 are formed, and at the same time, four spuriously multi-phased internal clocks are also formed, while an external clock 1 is temporarily latched by a latch flip-flop 2. Synchronization is made with one of the multi-phased internal clocks, and a synchronization clock 36 is generated to be supplied to other equipment. Hence the synchronization clock to communicate with the other equipment can be generated with a period shorter than those of the internal clocks. As a result, the communication with the other equipment can be executed at a higher speed.
JP62224625A 1987-09-08 1987-09-08 Asynchronous control system Pending JPS6468048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62224625A JPS6468048A (en) 1987-09-08 1987-09-08 Asynchronous control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62224625A JPS6468048A (en) 1987-09-08 1987-09-08 Asynchronous control system

Publications (1)

Publication Number Publication Date
JPS6468048A true JPS6468048A (en) 1989-03-14

Family

ID=16816638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62224625A Pending JPS6468048A (en) 1987-09-08 1987-09-08 Asynchronous control system

Country Status (1)

Country Link
JP (1) JPS6468048A (en)

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