JPS54122053A - Simulation method - Google Patents

Simulation method

Info

Publication number
JPS54122053A
JPS54122053A JP2950378A JP2950378A JPS54122053A JP S54122053 A JPS54122053 A JP S54122053A JP 2950378 A JP2950378 A JP 2950378A JP 2950378 A JP2950378 A JP 2950378A JP S54122053 A JPS54122053 A JP S54122053A
Authority
JP
Japan
Prior art keywords
main clock
group
circuit
logic
lagging behind
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2950378A
Other languages
Japanese (ja)
Inventor
Masami Kushihashi
Jiro Hisayuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP2950378A priority Critical patent/JPS54122053A/en
Publication of JPS54122053A publication Critical patent/JPS54122053A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To ravel problems accompanying an decrease in simulation rate by converting a sequential circuit, composed of a group of flip-flops operating by a main clock and clocks sent out lagging behind the main clock, into a combinatorial circuit.
CONSTITUTION: The logical simulation model of the logic network including a sequential circuit operating synchronizing with a main clock and a group of clocks sent out lagging behind the main clock is stored in an external memory and a main memory maintaining the hierarchy structure. In this simulating method, a cycle line is set to a point on a circuit where the logic state changing by the main clock and clocks lagging behind the main clock will not propagate within one-clock time any more, and the input group of the logic circuit partitioned by this cycle line is divided on a mounting unit; and the gate group at the branch destination of this devided input group is divided into several parts as a unit, and the logic simulation of each part is done from the input group to the output side in sequence on a level unit.
COPYRIGHT: (C)1979,JPO&Japio
JP2950378A 1978-03-15 1978-03-15 Simulation method Pending JPS54122053A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2950378A JPS54122053A (en) 1978-03-15 1978-03-15 Simulation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2950378A JPS54122053A (en) 1978-03-15 1978-03-15 Simulation method

Publications (1)

Publication Number Publication Date
JPS54122053A true JPS54122053A (en) 1979-09-21

Family

ID=12277879

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2950378A Pending JPS54122053A (en) 1978-03-15 1978-03-15 Simulation method

Country Status (1)

Country Link
JP (1) JPS54122053A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4744084A (en) * 1986-02-27 1988-05-10 Mentor Graphics Corporation Hardware modeling system and method for simulating portions of electrical circuits

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