JPS5694840A - Counter synchronous control system - Google Patents

Counter synchronous control system

Info

Publication number
JPS5694840A
JPS5694840A JP17367579A JP17367579A JPS5694840A JP S5694840 A JPS5694840 A JP S5694840A JP 17367579 A JP17367579 A JP 17367579A JP 17367579 A JP17367579 A JP 17367579A JP S5694840 A JPS5694840 A JP S5694840A
Authority
JP
Japan
Prior art keywords
counter
control
timing
reqt
clka
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17367579A
Other languages
Japanese (ja)
Other versions
JPS6242532B2 (en
Inventor
Masatake Iwato
Kazuhiro Hara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP17367579A priority Critical patent/JPS5694840A/en
Publication of JPS5694840A publication Critical patent/JPS5694840A/en
Publication of JPS6242532B2 publication Critical patent/JPS6242532B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/40—Monitoring; Error detection; Preventing or correcting improper counter operation

Abstract

PURPOSE:To produce the control pulse that is synchronized with the free running pulse, by setting the set value to a timing counter after prefetching the timing necessary for the start of a control counter and then starting the start control of the control counter. CONSTITUTION:With application of the start signal OPEN-REQT to the flip-flop (FF)13. The FFs14 and 15 are set to open the gates 5 and 6. Then the free counter 1 counts CLKA and CLKB. The start request signal START-REQT is applied to the AND8. And when a coincidence is obtained between the count value of the counter 1 and the set value of the timing counter 2, the FF16 is set by the output of the coincidence circuit 3. Accordingly, the FFs17 and 18 are cut, and the control counter 4 counts CLKA and CLKB. In this case, the counter 4 works exactly in the same state as the counter 1.
JP17367579A 1979-12-27 1979-12-27 Counter synchronous control system Granted JPS5694840A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17367579A JPS5694840A (en) 1979-12-27 1979-12-27 Counter synchronous control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17367579A JPS5694840A (en) 1979-12-27 1979-12-27 Counter synchronous control system

Publications (2)

Publication Number Publication Date
JPS5694840A true JPS5694840A (en) 1981-07-31
JPS6242532B2 JPS6242532B2 (en) 1987-09-09

Family

ID=15965008

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17367579A Granted JPS5694840A (en) 1979-12-27 1979-12-27 Counter synchronous control system

Country Status (1)

Country Link
JP (1) JPS5694840A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013247628A (en) * 2012-05-29 2013-12-09 Nec Access Technica Ltd Count value propagation circuit and count value propagation method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013247628A (en) * 2012-05-29 2013-12-09 Nec Access Technica Ltd Count value propagation circuit and count value propagation method

Also Published As

Publication number Publication date
JPS6242532B2 (en) 1987-09-09

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