JP2013247628A - Count value propagation circuit and count value propagation method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a count value propagation circuit and a count value propagation method that correctly propagate a counter value between circuits using different clock sources while suppressing an increase in circuit scale.SOLUTION: A count value propagation circuit 10 includes: a first counter 20 for acquiring a first control signal according to a first clock signal of an interval T1 and performing a count action depending on the first control signal; a second counter 30 for acquiring a second control signal according to a second clock signal of an interval T2 that is half the interval T1 or less, and performing a count action depending on the second control signal; state output means 40 for acquiring the first control signal according to the first clock signal and outputting a binary state signal depending on the first control signal; synchronization means 50 for outputting as a synchronization clock signal a signal of detection of the first clock signal according to the second clock signal; and propagation means 60 for recognizing the state signal according to the synchronization clock signal and outputting the second control signal of a length T2 depending on the state signal.

Description

  The present invention relates to a count value propagation circuit, and more particularly to a count value propagation circuit that propagates a binary count value based on a first clock source to a circuit that operates based on the first clock source.

  As a circuit that propagates a count value between circuits having different clock sources, for example, in Patent Document 1 and Patent Document 2, a binary count value is converted into a gray code and output, and a gray code converted with a different clock is captured. A technique for propagating back to binary code is disclosed.

  Further, Patent Document 3 discloses a technique for propagating a binary count value by providing two holding circuits with different acquisition timings on the acquisition side and selecting the side that holds the true value.

JP-A-10-0665545 Japanese Patent Laid-Open No. 10-215185 Japanese Patent Laid-Open No. 05-075584

  However, the techniques of Patent Documents 1-3 need to have conversion circuits and holding circuits for the number of bits of the count value, and the circuit scale increases.

  An object of the present invention has been made in view of the above problems, and a count value propagation circuit and a count that can correctly propagate a counter value between circuits using different clock sources while suppressing an increase in circuit scale. To provide a value propagation method.

  To achieve the above object, the first count value propagation circuit according to the present invention acquires a first control signal synchronized with the first clock signal based on the first clock signal output at the interval T1, and acquires the first control signal. The second control signal is acquired based on the first counter that performs the counting operation according to the first control signal and the second clock signal that is output every interval T2 that is ½ or less of the interval T1. A second counter that performs a counting operation according to the second control signal, a state output that acquires the first control signal based on the first clock signal and outputs a binary state signal according to the acquired first control signal Means for detecting a first clock signal based on the second clock signal and outputting it as a synchronized clock signal; acquiring a status signal based on the synchronized clock signal; and depending on the acquired status signal Comprising a propagation means for outputting a second control signal length T2, the.

  In order to achieve the above object, the second count value propagation circuit according to the present invention acquires the first control signal synchronized with the first clock signal based on the first clock signal output at the interval T1, and acquires the first control signal. The second control signal is acquired based on the first counter that performs the counting operation according to the first control signal and the second clock signal that is output every interval T2 that is ½ or less of the interval T1. A second counter that performs a counting operation according to the second control signal, a first control signal is acquired based on the first clock signal, and a pulse having a length that is ½ of T1 according to the acquired first control signal A state output means for outputting a signal; and a propagation means for detecting a rising edge of the pulse signal based on the second clock signal and outputting a second control signal corresponding to the detected pulse signal.

  To achieve the above object, a first count value propagation method according to the present invention acquires a first control signal synchronized with a first clock signal based on a first clock signal output at an interval T1, and acquires the first control signal. The second control signal is acquired based on the first counter that performs the counting operation according to the first control signal and the second clock signal that is output every interval T2 that is ½ or less of the interval T1. And a second counter that performs a counting operation according to the second control signal. The first count value propagation method acquires the first control signal based on the first clock signal, outputs a binary state signal corresponding to the acquired first control signal, and based on the second clock signal. The first clock signal is detected and output as a synchronized clock signal, a status signal is acquired based on the synchronized clock signal, and a second control signal having a length T2 corresponding to the acquired status signal is output.

  In order to achieve the above object, a second count value propagation method according to the present invention obtains and obtains a first control signal synchronized with the first clock signal based on a first clock signal output at an interval T1. The second control signal is acquired based on the first counter that performs the counting operation according to the first control signal and the second clock signal that is output every interval T2 that is ½ or less of the interval T1. And a second counter that performs a counting operation according to the second control signal. Then, the second count value propagation method acquires the first control signal based on the first clock signal, and outputs a pulse signal having a length of 1/2 of T1 corresponding to the acquired first control signal, Based on the second clock signal, the rising edge of the pulse signal is detected, and a second control signal corresponding to the detected pulse signal is output.

  The count value propagation circuit and the count value propagation method according to the present invention can correctly propagate the counter value between circuits using different clock sources while suppressing an increase in circuit scale.

1 is a block configuration diagram of a count value propagation circuit 10 according to a first embodiment of the present invention. 3 is a timing chart of the count value propagation circuit 10 according to the first embodiment of the present invention. It is a block block diagram of the count value propagation circuit 10B which concerns on the 2nd Embodiment of this invention. It is a timing chart of count value propagation circuit 10B concerning a 2nd embodiment of the present invention. It is a block block diagram of the count value propagation circuit 100 which concerns on the 3rd Embodiment of this invention. The operation of the pulse generator 400 according to the third embodiment of the present invention is represented by a state machine. It is a circuit diagram of the rising detector 500 which concerns on the 3rd Embodiment of this invention. It is a timing chart of the count value propagation circuit 100 according to the third embodiment of the present invention. 9 is an enlarged view of a part of a timing chart of a count value propagation circuit 100 according to a third embodiment of the present invention. It is a block block diagram of the count value propagation circuit 100B which concerns on the 4th Embodiment of this invention. The operation of the state signal generator 700B according to the fourth embodiment of the present invention is represented by a state machine. It is a circuit diagram of the status signal capture device 800B which concerns on the 4th Embodiment of this invention. It is a timing chart of count value propagation circuit 100B concerning a 4th embodiment of the present invention.

(First embodiment)
The count value propagation circuit according to the first embodiment will be described. FIG. 1 shows a block diagram of the count value propagation circuit according to the present embodiment. In FIG. 1, the count value propagation circuit 10 according to the present embodiment includes a first counter 20, a second counter 30, a state output unit 40, a synchronization unit 50, and a propagation unit 60.

  The first counter 20 is set with an initial value and a maximum value, acquires a first control signal based on a first clock signal output at an interval T1, and performs a counting operation according to the acquired first control signal. .

  In the present embodiment, the first clock signal and the first control signal are synchronized. The first control signal includes “reset 1”, “count up 1”, and “count down 1”, and when none of “reset 1”, “count up 1”, and “count down 1” is output, This is the first control signal for “stop”.

  In the present embodiment, the initial value “0” and the maximum value “5” are set in the first counter 20, and the first counter 20 acquires the first control signal when the first clock signal becomes HIGH. Then, according to the acquired first control signal, count operations of “return to initial value”, “+1”, “−1”, and “± 0 (count stop)” are performed.

  The second counter 30 is set with the same initial value and maximum value as the first counter 20, and is output from the propagation means 60 based on the second clock signal output at the interval T2 that is 1/2 or less of the interval T1. The second control signal is acquired, and a counting operation is performed according to the acquired second control signal. The second control signal corresponds to the first control signal, and includes “reset 2”, “count up 2”, “count down 2”, and “stop”.

  In the present embodiment, the second counter 30 is set with an initial value “0” and a maximum value “5”, acquires the second control signal when the second clock signal becomes HIGH, and acquires the acquired second control signal. In response to this, a count operation of “return to initial value”, “+1”, “−1”, “± 0 (count stop)” is performed.

  The state output means 40 acquires a first control signal based on the first clock signal, and outputs a binary state signal corresponding to the acquired first control signal. In the present embodiment, the state output means 40 receives the state signal “001” when the first control signal “reset 1” is acquired, and the state signal “010” when the “count up 1” is acquired. When the “countdown 1” is acquired, the state signal “100” is output, and when the “stop” first control signal is acquired, the state signal “000” is output.

  Here, when the first control signal is M types, the status signal is represented by a binary number of (M−1) bytes. In the present embodiment, there are four types of first control signals: “reset 1”, “count up 1”, “count down 1”, and “stop”, so the status signal is a binary number of (4-1) = 3 bytes. It is represented by

  The synchronization means 50 detects the rising edge of the first clock signal based on the second clock signal, and outputs the synchronized clock signal having the length T2 when the first clock signal is detected.

  The propagation unit 60 acquires the state signal output from the state output unit 40 based on the synchronization clock signal output from the synchronization unit 50, and a second control signal having a length T2 corresponding to the acquired state signal. Is output. Specifically, when the propagation unit 60 acquires the state signal “001” from the state output unit 40 based on the synchronization clock signal, the propagation unit 60 outputs the second control signal “reset 2”. Similarly, the propagation means 60 obtains “count up 2” when the state signal “010” is obtained, “count down 2” when the state signal “100” is obtained, and “count down 2” when the state signal “000” is obtained. The second control signal “stop” is output.

  FIG. 2 shows a timing chart of the count value propagation circuit 10 according to the present embodiment. In FIG. 2, the first clock signal is output at an interval T1, and the second clock signal is output at an interval T2 that is ½ or less of the interval T1. Further, the counter 1 has a count operation of the first counter 20 on the left side and a count value output from the first counter 20 on the right side.

  In FIG. 2, the first counter 20 holds a count value “1” at time t0. Then, when the first clock signal at time t1 becomes HIGH, the first counter 20 acquires the first control signal of “count up 1”, performs the count operation of “+1”, and performs the count value “2”. Is output. In addition, the first counter 20 acquires the first control signal “count up 1” at time t2, performs a count operation of “+1”, and outputs a count value “3”. Similarly, “reset 1” is acquired at time t3 and the initial value “0” is output, “countdown 1” is acquired at time t4 and the maximum value “5” is output, and any of the first values is output at time t5. Since the control signal is not acquired, the count operation of “± 0 (count stop)” is performed, and the same count value “5” as that at time t4 is output.

  The state output means 40 is in the stop state “000” at time t0. Then, when the first clock signal at time t1 becomes HIGH, the state output unit 40 acquires the first control signal “count up 1”, changes the state, and outputs the state signal “010”. . Similarly, the status output means 40 acquires “count up 1” at time t2, acquires the status signal “010”, acquires “reset 1” at time t3, and receives the status signal “001” at time t4. Since “countdown 1” is acquired and status signal “100” is acquired, and no first control signal is acquired at time t5, status signal “000” is output.

  On the other hand, the synchronization means 50 detects the rising edge of the first clock signal when the second clock signal becomes HIGH at time t01, and then synchronizes the synchronization clock at time t02 when the second clock signal becomes HIGH. Output a signal. The synchronizing means 50 detects LOW of the first clock signal when the second clock signal at time t02 becomes HIGH. Then, it detects that the first clock signal becomes HIGH at time t11, and outputs a synchronized clock signal having a length T2 at time t12. Similarly, the synchronization means 50 outputs a synchronization clock signal having a length T2 at time t22, time t32, time t42, and time t52.

  The propagation means 60 recognizes the state signal of the state output means 40 when the second clock signal becomes HIGH and the synchronized clock signal becomes HIGH, and corresponds to the recognized state signal and has the length T2. 2 Outputs a control signal. For example, in FIG. 2, the propagation means 60 recognizes the state signal “000” of the state output means 40 at time t03 when the synchronization clock signal becomes HIGH, and indicates the second control signal of “stop”. . Further, the propagation means 60 recognizes the state signal “010” at time t13 when the synchronization clock signal becomes HIGH, and outputs the second control signal of “count up 2” having the length T2. Further, the propagation means 60 recognizes the state signal “010” at time t23 and outputs the second control signal of “count up 2” having the length T2. Similarly, the propagation means 60 outputs a second control signal “reset 2” at time t33 and “countdown 2” at time t43.

  The second counter 30 acquires the second control signal output from the propagation means 60 based on the second clock signal, and performs a counting operation according to the acquired second control signal. In FIG. 2, the second counter 30 holds a count value “1” at time t0. Then, the second control signal is confirmed every time the second clock signal becomes HIGH. The second counter 30 acquires the second control signal “count up 2” at time t21, performs a count operation of “+1”, and outputs a count value “2”. In addition, the second counter 30 acquires the second control signal “count up 2” at time t31 and outputs the count value “3”. Similarly, the second counter 30 acquires “reset 2” at time t41 and outputs an initial value “0”, acquires “countdown 2” at time t51, and outputs a maximum value “5”. .

  As described above, in the count value propagation circuit 10 according to the present embodiment, the second counter 30 is delayed by 3 × interval T2 from the time when the second clock signal after the counter operation of the first counter 20 becomes HIGH. The same counter operation as that of the first counter 20 is performed. In the count value propagation circuit 10 according to the present embodiment, the synchronization means 50 detects the first clock signal for one cycle (interval T2), the synchronization clock signal output for one cycle (interval T2), and the propagation means 60 performs the first cycle. Since one cycle (interval T2) is required to output the two control signals, the counter operation of the first counter 20 can be propagated to the second counter 30.

In the above-described embodiment, the state signal is represented by a binary number of (M−1) bytes when there are M types of first control signals, but is not limited thereto. For example, when the first control signal is ^2M types, the status signal can also be represented by an M-byte binary number. That is, when the first control signal has 2 ² = 4 types, the status signal can also be represented by a 2-byte binary number. In this case, the state output means 40 changes the state signal “01” to “count up 1” and the state signal “10” to “count down 1” when the first control signal “reset 1” is acquired. On the other hand, a status signal “11” is output, and a status signal “00” is output for “stop”.

(Second Embodiment)
A second embodiment will be described. FIG. 3 shows a block configuration diagram of the count value propagation circuit according to the present embodiment. In FIG. 3, the count value propagation circuit 10B according to the present embodiment includes a first counter 20B, a second counter 30B, a state output unit 40B, and a propagation unit 60B.

  The first counter 20B and the second counter 30B are the same as the first counter 20 and the second counter 30 of FIG. 1 described in the first embodiment, and detailed description thereof is omitted. Also in this embodiment, the initial value “0” and the maximum value “5” are set for the first counter 20B and the second counter 30B. Further, the first clock signal is output at an interval T1, and the second clock signal is output at an interval T2 that is ½ or less of the interval T1.

  The state output means 40B acquires a first control signal based on the first clock signal, and outputs a pulse signal corresponding to the acquired first control signal. The status output means 40B acquires “reset pulse” when acquiring the “reset 1” first control signal, “count up pulse” when acquiring “count up 1”, and “count down 1”. In this case, a “countdown pulse” is output. The status output means 40B outputs a pulse signal having a length ½ times the interval T1.

  The propagation means 60B detects the rising edge of the pulse signal output from the state output means 40B based on the second clock signal, and when the pulse signal is detected, the detection is performed when the second clock signal becomes HIGH next time. A second control signal corresponding to the pulse signal thus output is output. In the present embodiment, the propagation means 60B detects the “reset 2” second control signal when the “reset pulse” is detected, and the “count up 2” second control signal when the “count up pulse” is detected. When the “countdown pulse” is detected, the second control signal “countdown 2” is output.

  FIG. 4 shows a timing chart of the count value propagation circuit 10B according to the present embodiment. In the following, the description will focus on the parts of the first embodiment that are different from FIG. In FIG. 4, the first counter 20B acquires the first control signal when the first clock signal becomes HIGH, and performs a counting operation according to the acquired first control signal. Then, the first counter 20B outputs count values of “1”, “2”, “3”, “0”, “5”, “5” from T0 to T5.

  The state output means 40B acquires the first control signal when the first clock signal becomes HIGH, and outputs a pulse signal corresponding to the acquired first control signal. In FIG. 4, the state output means 40B obtains the first control signal “count up 1” when the first clock signal becomes HIGH at time t1, and the “count up” corresponding to “count up 1”. "Up pulse" is output. Further, the status output means 40B obtains the “count-up 1” first control signal at time t2, thereby outputting “count-up pulse. Similarly, the status output means 40B outputs“ reset 1 at time t3. ”And“ reset pulse ”are output,“ countdown 1 ”is acquired and“ countdown pulse ”is output at time t4. Since the state output unit 40B does not acquire any first control signal at time t5, the state output unit 40B stops outputting the pulse signal.

  If the propagation means 60B detects the rising edge of the pulse signal when the second clock signal becomes HIGH, the propagation means 60B outputs a second control signal corresponding to the pulse signal detected when the second clock signal becomes HIGH next time. . In FIG. 4, the propagation means 60B detects the rise of the “count up pulse” at time t11, and then outputs the second control signal of “count up 2” at time t12 when the second clock signal becomes HIGH. Further, the propagation means 60B detects the rising of the “count up pulse” at time t21 and outputs “count up 2” at time t22. Similarly, the propagation means 60B detects “reset pulse” at time t31, detects “reset 2” at time t32, detects “countdown pulse” at time t41, and outputs “countdown 2” to T42.

  The second counter 30B holds the count value “1” at time t0. The second counter 30B acquires the second control signal output from the propagation means 60B at time t13, time t23, time t33, and time t43, and performs a counting operation according to the acquired second control signal. From time 03 to time t43, count values “1”, “2”, “3”, “0”, and “5” are output.

  As described above, in the count value propagation circuit 10B according to the present embodiment, the second counter 30B is delayed by 2 × interval T2 time from when the second clock signal after the counter operation of the first counter 20B becomes HIGH. Thus, the same counter operation as that of the first counter 20B is performed. The count value propagation circuit 10B according to the present embodiment requires only one cycle (interval T2) for detection of the pulse signal by the propagation means 60B and one cycle (interval T2) for the output of the second control signal. The counter operation can be propagated to the second counter 30B.

  When the state output unit 40B outputs a plurality of pulse signals according to the first control signal, the state output unit 40B performs processing in comparison with the state output unit 40 of the count value propagation circuit 10 according to the first embodiment. Although complicated, the counter operation of the first counter 20B can be quickly transmitted to the second counter 30B.

(Third embodiment)
A third embodiment will be described. FIG. 5 shows a block diagram of the count value propagation circuit according to the present embodiment. In FIG. 5, the count value propagation circuit 100 according to the present embodiment includes a first counter 200, a multiplier circuit 300, a pulse generator 400, a rising detector 500, and a second counter 600.

  The first counter 200 is a binary counter in which an initial value and a maximum value are set, and performs a counter operation based on the first control signal and the first clock signal. In the present embodiment, the first clock signal is output at an interval T1. The first control signal includes reset 1, count up 1, count down 1, and stop. The first counter 200 enters four states of “reset”, “count up”, “count down”, and “stop” based on the first control signal.

  The first counter 200 returns the count value to the initial value when the reset 1 is HIGH. The first counter 200 increments the count value when the reset 1 is LOW and the count-up 1 is HIGH. The first counter 200 decrements the count value when the reset 1 is LOW, the count-up 1 is LOW, and the count-down 1 is HIGH. When the count value becomes smaller than the minimum value by decrementing, the first counter 200 sets the count value to the maximum value. On the other hand, when the count value becomes larger than the maximum value by incrementing, the count value is set to the minimum value.

  The multiplier circuit 300 doubles the first clock signal and outputs a multiplied clock signal output at an interval twice the interval T1. As the multiplication circuit 300, a PLL (Phase-locked loop) can be applied.

  The pulse generator 400 operates based on the first control signal and the multiplied clock signal. The pulse generator 400 outputs the four states of the “reset”, “count up”, “count down”, and “stop” of the first counter 200 as a 3-bit pulse state signal with a Hamming distance “1”. .

  FIG. 6 shows the operation of the pulse generator 400 in a state machine. In the present embodiment, the first counter 200 is initially in a “stop” state. When the multiplied clock signal is HIGH and the reset 1 is HIGH, the pulse generator 400 transits to the “reset” state. When the multiplied clock signal is HIGH, the reset 1 is LOW, and the count-up 1 is HIGH, the pulse generator 400 transitions to the “count-up” state. Further, when the multiplied clock signal is HIGH, the reset 1 is LOW, the count up 1 is LOW, and the count down 1 is HIGH, the pulse generator 400 transitions to the “count down” state. When the multiplied clock signal becomes LOW, the pulse generator 400 transitions to the “stop” state.

  The pulse generator 400 outputs a pulse state signal corresponding to the transition state of the first counter 200 based on a multiplied clock signal that is a doubled clock signal of the first clock signal. That is, the pulse generator 400 outputs the pulse state signal “000” in the “stop” state, the pulse state signal “001” in the “reset” state, and the pulse state signal “000” in the “count up” state. When “010” is in the “countdown” state, the pulse state signal “100” is output.

  In this embodiment, since the pulse generator 400 operates based on a multiplied clock signal that is a doubled clock of the first clock signal, before the transition to the “reset”, “count up”, and “count down” states. Always return to the “stop” state. When the pulse generator 400 returns to the “stop” state before the transition, a pulse state signal having a Hamming distance of “1” is generated.

  The rising detector 500 operates based on the second clock signal output at an interval T2 that is equal to or less than ½ of the interval T1 of the first clock signal. In the present embodiment, the interval T2 is 1/4 of the interval T1. The rising detector 500 detects the rising edge by sampling the count-up pulse, the count-down pulse and the reset pulse output from the pulse generator 400 based on the second clock signal in two stages, and counts up 2, counts down 2 or reset 2 The second control signal is generated and output.

  An example of a circuit diagram of the rising detector 500 is shown in FIG. In FIG. 7, the rising detector 500 includes a countdown detector 510, a countup detector 520, and a reset detector 530. Each of countdown detection unit 510, countup detection unit 520, and reset detection unit 530 includes three flip-flop (FlipFlop) circuits, an inverting circuit, and an AND circuit.

  For example, the countdown detection unit 510 includes FF 511, FF 512, FF 513, inversion 514, and logical product 515. The countdown detector 510 receives the countdown pulse output from the pulse generator 400 based on the second clock signal, detects the rising edge of the countdown pulse, and outputs the second control signal for countdown2.

  The second counter 600 is a binary counter in which an initial value and a maximum value are set, and performs a counter operation based on the second control signal and the second clock signal output from the rising detector 500. Based on the second control signal, the second counter 600 is in four states: “reset”, “count up”, “count down”, and “stop”.

  The second counter 600 returns the count value to the initial value when the reset 2 is HIGH. The second counter 600 increments the count value when the reset 2 is LOW and the count-up 2 is HIGH. The second counter 600 decrements the count value when the reset 2 is LOW, the count-up 2 is LOW, and the count-down 2 is HIGH. When the count value becomes smaller than the minimum value by decrementing, the second counter 600 sets the count value to the maximum value. On the other hand, when the count value becomes larger than the maximum value by incrementing, the second counter 600 sets the count value to the minimum value.

  FIG. 8 shows a timing chart of the count value propagation circuit 100 according to the present embodiment. In FIG. 8, the counter 1 is a counter value output from the first counter 200, and the counter 2 is a counter value output from the second counter 600.

  First, the first counter 200 takes in the first control signal when the first clock signal is HIGH, and outputs a counter value in accordance with the fetched first control signal. In FIG. 8, the first counter 200 takes in the first control signal of reset 1 at time t1 and outputs a counter value of “0”. The first counter 200 takes in the first control signal of count-up 1 at time t2, increments it, and outputs a counter value of “1”. The first counter 200 takes in count-up 1 at time t3 and outputs a counter value of “2”, takes in count-down 1 at time t4, decrements and outputs a counter value of “1”.

  Then, the first counter 200 captures the first control signal based on the first clock signal, and thereby, between time t1 and time t12, “0”, “1”, “2”, “1”, “1”, “ The counter values of “0”, “6”, “0”, “1”, “2”, “3”, “4”, “5” are output. Since the first control signal is not input at time t13, the first counter 200 stops the counter operation and outputs the counter value “5” output at time t12 as it is.

  On the other hand, the pulse generator 400 outputs a pulse state signal corresponding to the first control signal when the multiplied clock signal output at an interval twice the interval T1 is HIGH. When the multiplied clock signal at time t1 becomes HIGH, the pulse generator 400 takes in the first control signal of reset 1 and transitions to the reset state, thereby outputting a reset pulse, and then returns to the stop state.

  In addition, the pulse generator 400 takes in the first control signal of count-up 1 at time t2 and transitions to the count-up state, and then returns to the stop state. Similarly, the pulse generator 400 takes in the first control signal when the multiplied clock signal becomes HIGH, outputs a pulse state signal corresponding to the taken-in first control signal, and returns to the stopped state.

  Then, the pulse generator 400 performs “reset pulse”, “count-up pulse”, “count-up pulse”, “count-down pulse”, “count-down pulse” for each half period of the interval T1 from time t1 to time t12. , “Countdown pulse”, “countup pulse”, “countup pulse”, “countup pulse”, “countup pulse”, “countup pulse”, “countup pulse” are output. Since the first control signal is not captured at time t13, no pulse state signal is output.

  The rising detector 500 detects the rising edge of the pulse state signal by sampling the pulse state signal output from the pulse generator 400 based on the second clock signal, and detects the rising edge of the pulse state signal based on the detected pulse state signal. 2 Generate and output control signals. FIG. 9 shows an enlarged view of the timing chart of FIG. 8 from time t1 to time t5.

  In FIG. 9, the rising detector 500 detects the rising edge of the reset pulse when the second clock signal becomes HIGH at time t0a, and resets the reset 2 when the second clock signal becomes HIGH again after the period T2. A second control signal is output. When the second clock signal becomes HIGH at time t0b, the reset pulse is maintained in the HIGH state. Therefore, the rising detector 500 does not detect the rising of the pulse state signal, and the reset 2 is reset at time t0c. Stop output. Similarly, rising detector 500 does not detect the rising of the pulse state signal at time t0c and time t0d, and does not output the second control signal at time t0d and time t1a.

  Then, the rising detector 500 detects the rising edge of the reset pulse again at time t1a, and outputs the second control signal for reset 2 at time t1b. The rise detector 500 does not detect the rise of the pulse state signal from time t1b to time t1d, and therefore does not output the second control signal from time t1c to time t2a. Similarly, rising detector 500 detects rising edges of count-up pulse, count-up pulse, and count-down pulse at time t2a, time t3a, and time t4a, respectively, and counts up at time t2b, time t3b, and time t4b, respectively. 2, the second control signal of count-up 2 and count-down 2 is output.

  On the other hand, in FIG. 9, the second counter 600 takes in the second control signal of reset 2 at time t0c and outputs a counter value of the initial value “0”. The second counter 600 takes in reset 2 at time t1c, outputs the initial value “0” again, takes in count-up 2 at time t2c, increments it, and outputs a counter value of “1”.

  Similarly, the second counter 600 takes in count-up 2 at time t3c and outputs a counter value of “2”, and takes down count-down 2 at time t4c and outputs a counter value of “1”.

  Then, as shown in FIG. 8, the second counter 600 is based on the acquired second control signal, “0”, “1”, “2”, “1”, “0”, “6”, “6”, “ The counter values of “0”, “1”, “2”, “3”, “4”, “5”, “5” are output.

  As shown in FIG. 8 and FIG. 9, the second counter 600 shifts in the same way as the first counter 200 by delaying two clocks and half of the second clock signal from the transition of the first counter 200. The same count value as that of the first counter 200 is output in four clock cycles.

  As described above, the count value propagation circuit 100 according to the present embodiment has a value significantly different from the count value for a binary counter in which the Hamming distance proceeds from 1 bit to all bit widths between circuits having different clock sources. Can be prevented from being propagated.

  In addition, the count value propagation circuit 100 according to the present embodiment can propagate the state of the counter as a pulse state signal regardless of the number of bits of the count value, thereby avoiding an increase in the circuit scale of the synchronization circuit. it can.

(Fourth embodiment)
A fourth embodiment will be described. FIG. 10 shows a block configuration diagram of the count value propagation circuit according to the present embodiment. In FIG. 10, the count value propagation circuit 100B according to the present embodiment includes a first counter 200B, a state signal generator 700B, a state signal fetcher 800B, and a second counter 600B.

  The first counter 200B operates in the same manner as the first counter 200 of the count value propagation circuit 100 described in the third embodiment. That is, the first counter 200B performs a counter operation based on the first control signal of count up 1, count down 1, reset 1, and the first clock signal output at the interval T1. Based on the first control signal, the first counter 200B is in four states of “reset”, “count up”, “count down”, and “stop”.

The status signal generator 700B operates based on the first control signal and the first clock signal. The status signal generator 700B represents the four states of “reset”, “count up”, “count down”, and “stop” based on the first control signal as a 2-bit conversion status signal. The conversion state signal can be represented by an M-byte binary number when the first control signal is ^2M types. In this embodiment, since there are four types of first control signals, that is, ²² types, the conversion state signal is represented by 2 bits.

  FIG. 11 shows the operation of the state signal generator 700B represented by a state machine. In FIG. 11, when the first clock signal is HIGH and the reset 1 is HIGH, the state signal generator 700B transitions to a “reset” state. When the first clock signal is HIGH, the reset 1 is LOW, and the count-up 1 is HIGH, the state signal generator 700B transitions to the “count-up” state. Further, when the first clock signal is HIGH, the reset 1 is LOW, the count up 1 is LOW, and the count down 1 is HIGH, the state signal generator 700B transitions to the “count down” state. When the first clock signal is HIGH, the reset 1 is LOW, the count-up 1 is LOW, and the count-down 1 is LOW, the state signal generator 700B transitions to the “stop” state.

  Then, the state signal generator 700B outputs a conversion state signal corresponding to the transition state. That is, the state signal generator 700B converts the conversion state signal “00” in the “stop” state, the conversion state signal “01” in the “reset” state, and the conversion state signal in the “count up” state. When “10” is in the “count down” state, the conversion state signal “11” is output.

  The state signal fetcher 800B operates based on the second clock signal output at an interval T2 different from the interval T1 of the first clock signal. In the present embodiment, the interval T2 is 1/4 of the interval T1. The state signal fetcher 800B takes in the first clock signal and the conversion state signal output from the state signal generator 700B when the second clock signal is HIGH, and generates and outputs a second control signal.

  Specifically, the status signal fetcher 800B outputs the synchronized clock signal when the second clock signal becomes HIGH next when the rising edge of the first clock signal is detected when the second clock signal is HIGH. In addition, a timing signal is output after a period T2 during which the synchronization clock signal is output.

  Further, the status signal fetcher 800B outputs the second control signal of the reset 2B, the count-up 2B or the count-down 2B generated from the fetched conversion status signal based on the synchronization clock signal.

  An example of a circuit diagram of the status signal fetcher 800B is shown in FIG. As shown in FIG. 12, the status signal fetcher 800B includes FF 810B, FF 820B, FF 830B, an inverting circuit 840B, an AND circuit 850B, FF 860B, FF 870B, FF 880B, and a decode 890B.

  The status signal fetcher 800B detects the rising edge of the first clock signal based on the second clock signal using the FFs 810B, 820B, 830B, the inverting circuit 840B, and the AND circuit 850B, and then the second clock signal When the signal becomes HIGH, a synchronization clock signal is output from the AND circuit 850B. The synchronized clock signal output from the AND circuit 850B is delayed by one clock (interval T2) of the second clock signal in the FF 880B and output to the decode 890B as a timing signal.

  On the other hand, the status signal fetcher 800B uses the FF 860B to capture the conversion status signal based on the second clock signal and the FF 870B captures the conversion status signal captured based on the synchronized clock signal output from the AND circuit 850B. And output to the decode 890B as a synchronization state signal.

  In the decode 890B, when the timing signal is HIGH, the second control signal generated from the captured synchronization state signal is output. That is, when the synchronization state signal is “11”, the second control signal of countdown 2 is output, and when the synchronization state signal is “10”, the second control signal of countup 2 is output and the synchronization state signal is output. When the signal is “01”, the second control signal of reset 2 is output. The status signal fetcher 800B takes the output timing of the synchronization status signal by delaying the synchronization clock signal by one clock of the second clock signal and outputting the timing signal. In FIG. 12, it is considered that the number of stages of the FF circuit for capturing the conversion state signal and the FF circuit for capturing the first clock signal need not be the same clock edge.

  The second counter 600B performs a counter operation based on the second control signal and the second clock signal output from the status signal fetcher 800B. The second counter 600B performs “reset”, “count up”, “count down”, and “stop” counting operations based on the second control signal.

  FIG. 13 shows a timing chart of the count value propagation circuit 100B according to this embodiment. In FIG. 13, the first counter 200B is changed from time t1 to time t13 based on the first control signals of reset 1, count up 1 and count down 1 as in the case of the first counter 200 described in the third embodiment. , “0”, “1”, “2”, “1”, “0”, “6”, “0”, “1”, “2”, “3”, “4”, “5”, “ 5 "is output.

  Based on the first control signal and the first clock signal, the state signal generator 700B outputs a conversion state signal representing four states of “reset”, “count up”, “count down”, and “stop”. In FIG. 13, the status signal generator 700B converts the conversion status signal “reset: 01” after time t0, “count up: 10” after time t2, “count down: 11” after time t4, and after time t7. Then, a conversion state signal of “count up: 01” and “stop: 00” is output after time t13.

  When the state signal fetcher 800B detects the rising edge of the first clock signal when the second clock signal becomes HIGH, the status signal fetcher 800B outputs the synchronized clock signal when the second clock signal becomes HIGH next, and The timing signal is output after the period T2. That is, as shown in FIG. 13, the synchronization clock signal is output after a period of 1.5 × T2 has elapsed from the first clock signal, and the timing signal is output after the period of 2.5 × T2 has elapsed.

  The status signal fetcher 800B fetches the conversion status signal when the synchronization clock signal becomes HIGH, and resets 2, counts up 2 or counts down depending on the conversion status signal fetched when the timing signal becomes HIGH. 2nd control signal is output. That is, in FIG. 13, the conversion state signal in the reset state (01) is captured when the synchronization clock signal after time t0 becomes HIGH, and the second control signal of reset 2 when the timing signal becomes HIGH after the period T2. Is output. Similarly, the state signal fetcher 800B takes in the conversion state signal in the count-up state (10) when the synchronization clock signal after time t2 becomes HIGH, and counts when the timing signal becomes HIGH after the period T2. Output up 2.

  The second counter 600B takes in the second control signal output from the state signal fetcher 800B when the second clock signal is HIGH, and outputs a counter value corresponding to the fetched second control signal. In FIG. 13, the second counter 600B outputs a counter value of “0” by taking in the second control signal of reset 2 after time t0. The second counter 600B increments by taking in the second control signal of count-up 2 when the second clock signal after time t2 becomes HIGH, and outputs a counter value of “1”. Similarly, the second counter 600B takes in count-up 2 after time t3 and outputs a counter value of “2”, takes in count-down 2 after time t4, and decrements and outputs a counter value of “1”. To do.

  Then, the second counter 600B, based on the captured second control signal, “0”, “1”, “2”, “1”, “0”, “6”, “0”, “1”, The counter values “2”, “3”, “4”, “5”, “5” are output.

  As shown in FIG. 13, the second counter 600B performs a counter operation similar to that of the first counter 200B by performing a counter operation similar to that of the first counter 200B by delaying three clocks and half of the second clock signal from the counter operation of the first counter 200B. The same count value as that of the first counter 200B is output in four clock cycles.

  As described above, the count value propagation circuit 100B according to the present embodiment does not need to generate a doubled signal of the first clock signal by using the first clock signal after being oversampled. Further, since the number of bits of the state signal to be propagated can be minimized, the circuit can be made smaller than the count value propagation circuit 100 of FIG. 5 described in the third embodiment. However, since the first clock signal is a clock line and the conversion state signal is a data line, it is difficult to adjust the delay. Therefore, the count value propagation circuit 100B according to the present embodiment is preferably applied to a system with a small number of receiving sides. .

  Note that the present invention is not limited to the above-described embodiment, and any design change or the like within a range not departing from the gist of the present invention is included in the present invention.

10, 10B count value propagation circuit 20, 20B first counter 30, 30B second counter 40, 40B status output means 50 synchronization means 60, 60B propagation means 100, 100B count value propagation circuit 200, 200B first counter 300 multiplication circuit 400 Pulse generator 500 Rising detector 600, 600B Second counter 700B Status signal generator 800B Status signal fetcher

Claims (9)

A first counter that acquires a first control signal synchronized with the first clock signal based on a first clock signal output at an interval T1, and performs a counting operation according to the acquired first control signal;
A second counter that acquires a second control signal based on a second clock signal that is output every interval T2 that is ½ or less of the interval T1, and that performs a counting operation according to the acquired second control signal;
Status output means for acquiring the first control signal based on the first clock signal and outputting a binary status signal corresponding to the acquired first control signal;
Synchronization means for detecting the first clock signal based on the second clock signal and outputting the detected signal as a synchronization clock signal;
Propagation means for obtaining the state signal based on the synchronized clock signal and outputting the second control signal having a length T2 corresponding to the obtained state signal;
A count value propagation circuit comprising: The first control signal has M types,
The status signal is represented by a binary number of (M−1) bytes with a Hamming distance of 1.
The count value propagation circuit according to claim 1. The first control signal has ^2M types,
The status signal is represented by a binary number of M bytes.
The count value propagation circuit according to claim 1. 4. The count value propagation circuit according to claim 1, wherein the synchronization unit detects the first clock signal using a flip-flop circuit, an inverting circuit, and a logical product circuit. 5. The first control signal has four types of reset, count up, count down and stop,
An initial value and a maximum value are set in the first counter, and count operations of +1, −1, and ± 0 are performed to return to the initial value according to the first control signal, respectively, and at the position of the maximum value. When the first control signal indicating the count-up is acquired, the initial value is obtained, and when the first control signal indicating the count-down is acquired at the position of the initial value, the maximum value is obtained.
The count value propagation circuit according to any one of claims 1 to 4. A first counter that acquires a first control signal synchronized with the first clock signal based on a first clock signal output at an interval T1, and performs a counting operation according to the acquired first control signal;
A second counter that acquires a second control signal based on a second clock signal that is output every interval T2 that is equal to or less than ½ of the interval T1, and that performs a counting operation according to the acquired second control signal;
State output means for acquiring the first control signal based on the first clock signal and outputting a pulse signal having a length of ½ of T1 according to the acquired first control signal;
Propagation means for detecting a rising edge of the pulse signal based on the second clock signal and outputting the second control signal in accordance with the detected pulse signal;
A count value propagation circuit comprising: 7. The count value propagation circuit according to claim 6, wherein the propagation means detects a rising edge of the pulse signal using a flip-flop circuit, an inverting circuit, and a logical product circuit. A first counter that acquires a first control signal synchronized with the first clock signal based on a first clock signal output at an interval T1, and performs a counting operation according to the acquired first control signal;
A second counter that acquires a second control signal based on a second clock signal that is output every interval T2 that is equal to or less than ½ of the interval T1, and that performs a counting operation according to the acquired second control signal;
A count value propagation method using
Acquiring the first control signal based on the first clock signal, and outputting a binary state signal corresponding to the acquired first control signal;
Detecting the first clock signal based on the second clock signal, and outputting the detected signal as a synchronized clock signal;
Acquiring the state signal based on the synchronized clock signal and outputting the second control signal having a length T2 corresponding to the acquired state signal;
Count value propagation method. A first counter that acquires a first control signal synchronized with the first clock signal based on a first clock signal output at an interval T1, and performs a counting operation according to the acquired first control signal;
A second counter that acquires a second control signal based on a second clock signal that is output every interval T2 that is ½ or less of the interval T1, and that performs a counting operation according to the acquired second control signal;
A count value propagation method using
Acquiring the first control signal based on the first clock signal, and outputting a pulse signal having a length of ½ of T1 according to the acquired first control signal;
Detecting the rising edge of the pulse signal based on the second clock signal and outputting the second control signal according to the detected pulse signal;
Count value propagation method.

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