CN205247370U - Generation of random number device - Google Patents
Generation of random number device Download PDFInfo
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- CN205247370U CN205247370U CN201520820959.XU CN201520820959U CN205247370U CN 205247370 U CN205247370 U CN 205247370U CN 201520820959 U CN201520820959 U CN 201520820959U CN 205247370 U CN205247370 U CN 205247370U
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Abstract
The utility model relates to a generation of random number device. The device includes: adjustable delay module for postpone first clock signal, generate n the 2nd clock signal, adjust the 2nd individual clock signal's of n delay under control signal's control, storage module, including n level memory cell, n level memory cell includes the 1st grade of memory cell, intermediate stage memory cell and n level memory cell, synchronous logic modules for synchronization is carried out in output to n level memory cell, postpone the control logic module for according to n level memory cell's stable output, generate control signal, true random number is generated and exported. The utility model discloses be used for improving the output emergence metastable possibility of trigger, realize generating true random number according to the metastable state of trigger output, and need not adopt special clock to produce the complexity of asynchronous input signal, reduction chip.
Description
Technical field
The utility model relates to digital circuit field, relates in particular to a kind of random number generating apparatus.
Background technology
In digital synchronous circuits, often adopt trigger or latch as memory cell, these two kinds of devicesAll define the sequential requirement of a signal, only had to have met this sequential and require these two kinds of devices just canCorrectly to obtain (capture) data at input, to produce data at output. These two kinds of devices allEasily enter metastable state, so-called metastable state refers to that trigger or latch cannot be in certain stipulated time sectionsReach a certifiable state. In the time that trigger or latch enter metastable state, both unpredictable touchingThe output level of hair device or latch, also when unpredictable trigger or latch output stablizeOn certain correct level. In the meantime, trigger or latch are exported some intergrade level,Or may be in oscillatory regime, and these intergrade level can touch along each in signalling channelHair device or latch cascade formula are propagated down. Introduce metastable situation below as an example of trigger example, rightBe suitable for too in latch.
In order to ensure the reliability operating in trigger, input signal must stablize one before clock edgeThe section time, be generally defined as during this period of time trigger Ts Time Created, and input signal is on clock edgeAlso to continue afterwards to stablize a period of time, will be defined as during this period of time trigger retention time Th, thenThrough output time delay, (clocktooutput is called for short: output signal Tco) trigger. An if numberThe number of it is believed that does not meet the requirement of trigger Ts Time Created and retention time Th in the time changing, and triggersJust may there is metastable situation in the output of device.
As shown in Figure 1, be sequential chart when trigger normal condition in prior art, particularly,In Fig. 1 (a), input signal A is stable and when being greater than trigger and setting up before rising edge clockBetween Ts, and after the rising edge clock stabilization time be greater than trigger retention time Th, now touchThe output of hair device there will not be metastable state, the value of trigger output signal etc. after output time delay TcoIn input signal A. Wherein, if input signal and clock signal are asynchronous, this input signal is called againAsynchronous input signal, the transitional period (transition) be asynchronous input signal by A in B change procedureTransit time, in this transition process, the value of asynchronous input signal is uncertain; At figureIn 1 (b), similar with Fig. 1 (a), asynchronous input signal B is stable before rising edge clockAnd be greater than trigger Ts Time Created, when be greater than trigger maintenance stabilization time after rising edge clockBetween Th, the now output of trigger there will not be metastable state, after output time delay Tco, trigger is defeatedThe value that goes out signal equals asynchronous input signal B. As shown in Figure 2, for trigger in prior art occursSequential chart when metastable state, different from Fig. 1, in the figure, asynchronous input signal is on clockRise along before just change to B by A, but steady before rising edge clock of asynchronous input signal BFix time and be less than trigger Ts Time Created, and A just finished before rising edge clock, instituteCan be considered as negative value stabilization time after the rising edge clock of A, and this negative value is less than trigger requirementRetention time Th, so in this case, may there are metastable feelings in the output of triggerCondition, and after metastable state settles out, the output of trigger may be asynchronous input signal A, also canCan be asynchronous input signal B, be random, it doesn't matter with asynchronous input signal. Trigger existsAfter experience metastable state, which value is output valve specifically can be stabilized in, and is subject to flip-flop circuit design, manufacturesThe impact of multiple factors such as process deviation, circuit environment temperature, noise, this uncertainty can be doneFor true random number source. For trigger, there is metastable possibility lower, its as very withThe quality of the random number that the machine source of counting generates is just lower.
Known according to the sequential chart of Fig. 1 and Fig. 2, if the asynchronous input signal of trigger input existsIn the front and back Ts+Th time on trigger clock edge, keep stable, namely asynchronous input signal existsTs+Th time window does not change, and trigger just metastable state can not occur so, and now trigger is defeatedGo out be completely specified, there is no randomness; And only in the time of the front and back Ts+Th on trigger clock edgeBetween in window, if variation has occurred asynchronous input signal, just likely there is metastable state in the output of trigger.For example, but under advanced semiconductor technology, Ts+Th time window is very little: 0.1ns, evenLess, the cycle of supposing so trigger clock is 50ns, and asynchronous input signal is in the time of Ts+Th soBetween the possibility that changes in window be only: 0.1ns*100%/50ns=0.2%. Therefore, this situationIt is very little to there is metastable possibility in the output of lower trigger, and possibility is 0.2% when maximum, mayProperty hour is zero substantially.
In addition, in chip circuit design, asynchronous input signal often needs specific clock source to produceRaw, for example: need the larger clock of shake to produce asynchronous input signal, so produce asynchronous defeatedThe difficulty that enters signal is larger, also can increase the complexity of chip; And due to this asynchronous input signalClock and the clock of trigger be incoherent two clocks, between these two clocks, may be asynchronousSituation, may be also synchronous situation, this is unpredictable, in this case this asynchronous inputSignal can not be accomplished with trigger clock completely asynchronous, so the variation of this asynchronous input signal and triggeringThe clock of device, along " resonance " phenomenon that may be correlated with, will greatly reduce asynchronous input like thisThe possibility that signal changes in Ts+Th time window, thus the output of trigger further reducedThere is metastable possibility.
Utility model content
The utility model provides a kind of random number generating apparatus, occurs sub-in order to improve the output of triggerThe possibility of stable state, realizes according to the metastable state of trigger output and generates true random number, and need not adoptWith special clock generating asynchronous input signal, reduce the complexity of chip.
The utility model provides a kind of random number generating apparatus, comprising:
Adjustable delay module, for the first clock signal is postponed, generates n second clock letterNumber, under the control of control signal, the delay of described n second clock signal is adjusted, wherein,Described n second clock signal increases successively with respect to the delay of described the first clock signal, and n is largeIn or equal 3 natural number;
Memory module, comprises n level memory cell, and described n level memory cell comprises that the 1st grade of storage is singleUnit, intergrade memory cell and n level memory cell, described n second clock signal and the 3rd o'clockClock signal, respectively as input signal and the clock signal of described n level memory cell, makes the described the 1stLevel memory cell and described n level memory cell are output as normal condition, and described intergrade storage is singleIn unit, have at least one-level memory cell to be output as metastable state, described the first clock signal and the described the 3rdClock signal is synchronizing signal;
Synchronous logic module, for the output of described n level memory cell is carried out synchronously, to obtainThe stable output of described n level memory cell, eliminates described metastable state;
Postpone control logic module, for according to the stable output of described n level memory cell, generateDescribed control signal, generates and exports true random number.
In the utility model, adjustable delay module postpones the first clock signal, generates nSecond clock signal is adjusted the delay of n second clock signal under the control of control signal,Wherein, n second clock signal increases successively with respect to the delay of the first clock signal, n for being greater than orEqual 3 natural number, n second clock signal and the 3rd clock signal are respectively as n in memory moduleInput signal and the clock signal of level memory cell, make the 1st grade of memory cell and the storage of n level singleUnit is output as normal condition, and in intergrade memory cell, having one-level memory cell at least is metastable state,Then by synchronous logic module, the output of n level memory cell is carried out synchronously, obtained the storage of n level singleThe stable output of unit, eliminates aforesaid metastable state, finally postpones control logic module and deposits according to n levelThe stable output of storage unit generates control signal, generates and export true random number, like this, and owing to adoptingWith the first clock signal and the 3rd clock signal be synchronizing signal, so can avoid adopting asynchronous defeatedSituation that can not be completely asynchronous with the clock of memory cell while entering signal, the output that has improved memory cellThere is metastable possibility, realize according to the metastable state of trigger output and generate true random number, protectDemonstrate,prove the randomness of the true random number obtaining, and need not adopt special clock generating asynchronous input signal,Easily realize, reduced the complexity of chip.
Brief description of the drawings
Fig. 1 is sequential chart when trigger normal condition in prior art;
Fig. 2 is sequential chart when trigger generation metastable state in prior art;
Fig. 3 is the structural representation of the utility model random number generating apparatus embodiment;
Fig. 4 is the first exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Fig. 5 is n level d type flip flop in Fig. 4 example of the utility model random number generating apparatus embodimentThe rising edge of the 3rd clock signal of D input and the rising edge of the second clock signal of clock endRelativeness;
Fig. 6 is the second exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Fig. 7 is n level d type flip flop in Fig. 6 example of the utility model random number generating apparatus embodimentThe trailing edge of the 3rd clock signal of D input and the rising edge of the second clock signal of clock endRelativeness;
Fig. 8 is the 3rd exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Fig. 9 is n level d type flip flop in Fig. 8 example of the utility model random number generating apparatus embodimentThe rising edge of second clock signal of D input and the rising edge of the 3rd clock signal of clock endRelativeness;
Figure 10 is the 4th exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Figure 11 is that in Figure 10 example of the utility model random number generating apparatus embodiment, n level D triggersThe trailing edge of the trailing edge of the 3rd clock signal of the D input of device and the second clock signal of clock endRelativeness;
Figure 12 is the 5th exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Figure 13 is that in Figure 12 example of the utility model random number generating apparatus embodiment, n level D triggersThe trailing edge of the rising edge of the 3rd clock signal of the D input of device and the second clock signal of clock endRelativeness;
Figure 14 is the 6th exemplary construction schematic diagram of the utility model random number generating apparatus embodiment;
Figure 15 is that in Figure 14 example of the utility model random number generating apparatus embodiment, n level D triggersThe trailing edge of the trailing edge of the second clock signal of the D input of device and the 3rd clock signal of clock endRelativeness;
Figure 16 is the reality that adopts 5 grades of d type flip flops in the utility model random number generating apparatus embodimentThe circuit timing diagram of example.
Detailed description of the invention
Below in conjunction with specification drawings and specific embodiments, the utility model will be further described.
As shown in Figure 3, be the structural representation of the utility model random number generating apparatus embodiment, shouldDevice can comprise: memory module 31, adjustable delay module 32, synchronous logic module 33 and delayControl logic module 34, memory module 31 is connected with adjustable delay module 32, synchronous logic module 33Be connected with memory module 31, postpone control logic module 34 and be connected with synchronous logic module 33, postponeControl logic module 34 is connected with adjustable delay module 32. Wherein, memory module 31 can comprise nLevel memory cell, this n level memory cell specifically can comprise: the 1st grade of memory cell 311, centreLevel memory cell 312 and n level memory cell 313, intergrade memory cell 312 and the 1st grade are depositedStorage unit 311 connects, and n level memory cell 313 is connected with intergrade memory cell 312, wherein,N is more than or equal to 3 natural number, so intergrade memory cell 312 has n-2 storage singleUnit. The 1st grade of memory cell 311, intergrade memory cell 312 and n level memory cell 313All be connected with adjustable delay module 32, synchronous logic module 33 and the 1st grade of memory cell 311, inIntercaste memory cell 312 is all connected with n level memory cell 313.
In the present embodiment, adjustable delay module 32, for the first clock signal is postponed, generatesN second clock signal carries out the delay of n second clock signal under the control of control signalAdjust, wherein, n second clock signal increases successively with respect to the delay of the first clock signal, nFor being more than or equal to 3 natural number; N second clock signal and the 3rd clock signal are respectively as depositingIn storage module 31, input signal and the clock signal of n level memory cell, make the 1st grade of memory cell311 and n level memory cell 313 be output as normal condition, in intergrade memory cell 312 extremelyRare one-level memory cell is output as metastable state, the first clock signal with the 3rd clock signal for synchronizeingSignal; Synchronous logic module 33 is specifically connected with the output of n level memory cell, for to the storage of n levelThe output of unit is carried out synchronously, to obtain the stable output of n level memory cell, eliminates aforesaidMetastable state, like this, if while there is metastable state in the output of the memory cell of certain one-level, can be at synchronous logicIn module 33, make the state of the uncertain vibration of this grade of memory cell output obtain after stable carrying out againOutput, can make follow-up delay control logic module 34 judge soundly to obtain very random like thisNumber; Postpone control logic module 34 for according to the stable output of n level memory cell, generate and controlSignal, generates and exports true random number.
The specific works process of this embodiment is as follows: adjustable delay module 32 is carried out the first clock signalPostpone, generate n second clock signal, under the control of control signal to n second clock signalDelay adjust, wherein, n second clock signal complied with respect to the delay of the first clock signalInferior increase, n is more than or equal to 3 natural number; Memory module 31 by n second clock signal andThe 3rd clock signal, respectively as input signal and the clock signal of n level memory cell, makes the 1st gradeMemory cell 311 and n level memory cell 313 are output as normal condition, intergrade memory cellIn 312, have at least one-level memory cell to be output as metastable state, wherein, n level memory cell comprises the 1stLevel memory cell 311, intergrade memory cell 312 and n level memory cell 313, the first clock lettersNumber with the 3rd clock signal be synchronizing signal; Synchronous logic module 33 is entered the output of n level memory cellRow is synchronous, to obtain the stable output of n level memory cell, eliminates aforesaid metastable state; PostponeThe stable output of 34 n level memory cell of control logic module generates control signal, generates and exportsTrue random number.
In the present embodiment, adjustable delay module 32 postpones the first clock signal, generates nIndividual second clock signal is adjusted the delay of n second clock signal under the control of control signalWhole, wherein, n second clock signal increases successively with respect to the delay of the first clock signal, and n is largeIn or equal 3 natural number, n second clock signal and the 3rd clock signal are respectively as storage mouldInput signal and the clock signal of n level memory cell in piece 31, make the 1st grade of memory cell 311Be output as normal condition with n level memory cell 313, in intergrade memory cell 312, have at leastOne-level memory cell is metastable state, then defeated to n level memory cell by synchronous logic module 33Go out to carry out synchronously, to obtain the stable output of n level memory cell, eliminate aforesaid metastable state, lastPostpone control logic module 34 and generate control signal according to the stable output of n level memory cell, generateAnd export true random number, like this, due to adopt the first clock signal with the 3rd clock signal for synchronizeingSignal, so can not be completely asynchronous with the clock of memory cell can avoid adopting asynchronous input signal timeSituation, there is metastable possibility in the output that has improved memory cell, realizes defeated according to triggerThe metastable state that goes out end generates true random number, has ensured the randomness of the true random number obtaining, and need not adoptWith special clock generating asynchronous input signal, easily realize, reduce the complexity of chip.
Alternatively, in the present embodiment, the first clock signal and the 3rd clock signal can be sameClock signal; Or the 3rd clock signal is to obtain after the first clock signal carries out processing without delay logicThe clock signal arriving, for example, carries out to the first clock signal the clock signal that inversion operation obtains.
Alternatively, in the present embodiment, the first clock signal can be generated by clock source, in reality,The first clock signal can be generated by a clock source, and random number generating apparatus is to this clock sourceLowest operating frequency, frequency jitter and phase jitter all do not have particular/special requirement. Wherein, trembling of frequencyMove and can comprise the shake of maximum clock frequency and the shake of minimum clock frequency, the shake of phase place canComprise the shake of maximum clock frequency and the shake of minimum clock frequency. Alternatively, when this random number is rawWhen apparatus for converting is used for chip, the first clock signal can be generated by the clock source of chip internal, also canTo be generated by the clock chip of chip exterior.
Alternatively, in the present embodiment, then schematic diagram shown in Figure 3, this random number generates dressPut and can also comprise input delay module 35, input delay module 35 is for pressing the first clock signalPostpone according to second scheduled time, the first clock signal after input delay module 35 is divided into twoRoad is input to respectively memory module 31 and adjustable delay module 32. By input delay module 35 toOne clock signal postpones, and can guarantee to be input in memory module 31 and adjustable delay module 32Two paths of signals synchronous.
Alternatively, in the present embodiment, n level memory cell can be n level trigger; The storage of n level is singleUnit can also be n level latch. Wherein, n level trigger is specifically as follows n level d type flip flop, alsoIt can be the triggering of the other types such as n level JK flip-flop, n level T trigger or n level rest-set flip-flopDevice.
Alternatively, in the present embodiment, postponing control logic module 34 specifically can be for according to the 1The level stable output of memory cell 311 and the stable output of n level memory cell 313, generateControl signal, wherein, when stable output 311 and the n level memory cell of the 1st grade of memory cell313 stable output be not expect clock change along time, generate represent increase or reduce postponeControl signal. Like this, can obtain the input of every one-level memory cell of expection and clock end timeClock changes the relativeness on edge, thereby can ensure that metastable state phenomenon occurs intergrade memory cell 312,Be conducive to the generation of follow-up true random number.
Alternatively, in the present embodiment, the clock of clock signal changes along being specifically as follows rising edge,Also can be trailing edge, accordingly, if adopt rising edge trigger, the rising edge of clock signal hasEffect, if adopt trailing edge trigger, the trailing edge of clock signal is effective.
Alternatively, in the present embodiment, adjustable delay module 32 can comprise that the n that is connected in series is prolongedLate unit, 1 second clock signal of each delay cell output, in n delay cell the 1stThe delay of delay cell is adjusted under the control of control signal, generates the 1st second clock signal.N-1 delay cell except the 1st delay cell, be the time delay of each delay cellOne scheduled time, this n-1 delay cell is entered the second clock signal of the 1st delay cell outputRow postpones for n-1 time, obtains n the second clock increasing successively with respect to the delay of the first clock signalSignal, be aforesaid first scheduled time time delay each time, thus it is single to have realized the storage of n levelThe time that in unit, every one-level memory cell changes edge through calendar clock except the 1st grade of memory cell 311 is equalPostponed for first scheduled time than upper level trigger. Alternatively, first scheduled time can be according at randomNumber generating apparatus condition of work change, for example: according to the operating temperature of random number generating apparatus,The variation of voltage or fabrication process parameters and changing, and the rule of this variation and n level memory cell defeatedThe Time Created, the retention time that enter signal change according to the condition of work of random number generating apparatusRule is consistent, for example: Time Created, the retention time basis of n level memory cell input signal are randomCount the rising of generating apparatus operating temperature and increase, first scheduled time is according to random number generating apparatusThe rising of operating temperature is also to increase.
Alternatively, in the present embodiment, n second clock signal is as the clock of n level memory cellSignal, the 3rd clock signal is as the input signal of n level memory cell, in adjustable delay module 32The output of n delay cell connects respectively the clock end of n level memory cell, by postponing control logicModule 34 is exported the transmission delay of control signal control adjustable delay module 32, like this, and the each the 3rdThe clock of clock signal changes along the input that can be added in n level memory cell simultaneously, but every one-level is depositedThe clock of the clock end experience of storage unit changes along postponing for first scheduled time than upper level trigger,Thereby the input of every one-level memory cell and the clock of clock end are changed along having relative passSystem.
As shown in Figure 4, for the first exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, in this example, the first clock signal and the 3rd clock signal are same clock signal, nLevel memory cell is specially n level d type flip flop, and accordingly, the 1st grade of memory cell 311 is specially the1 grade of d type flip flop, intergrade memory cell 312 is specially intergrade d type flip flop, the storage of n levelUnit 313 is specially n level d type flip flop, and this n level d type flip flop is rising edge trigger,In adjustable delay module 32 successively connect n delay cell output respectively with n level d type flip flopClock end connect, the output of every one-level d type flip flop is connected with synchronous logic 33, remove the 1stFirst scheduled time of n-1 delay units delay beyond delay cell is specially Δ T, d type flip flopQ end be output.
The specific works process of this example is as follows: first the first clock signal passes through input delay module 35After postponing for second scheduled time, obtain the first clock signal after postponing, this first clock signal is divided into twoRoad, the D input of a road input n level d type flip flop, the rising edge of each like this 3rd clock signalCapital is added in the D input of n level d type flip flop simultaneously; Another road is input to adjustable delay module 32,Then n the second clock signal obtaining after postponing is input to successively n level D by adjustable delay module 32The clock end of trigger, so the second clock signal that the clock end of n level d type flip flop experiences is upperThe time that rises edge is different, and the 1st grade of d type flip flop is the rising edge that experiences the earliest second clock signal, then since the 2nd grade of d type flip flop until n level d type flip flop, every one-level D triggersThe time of the rising edge of the clock end experience second clock signal of device all than previous stage d type flip flop timeFirst scheduled time of the time delay Δ T of the rising edge of clock end experience clock signal, here, first is pre-Fix time is exactly that the rising edge of second clock signal is during from the transmission that is input to output of a delay cellBetween; Synchronous logic module 33 receives the output of n level d type flip flop, defeated to this n level d type flip flopGo out to carry out synchronously, to make the stable output of this n level d type flip flop, eliminate the output of this n level d type flip flopThe metastable state that end may occur; Postpone control logic module 34 according to output in synchronous logic module 33The stable output signal of n level d type flip flop, generate control signal, control adjustable delay module 32In time delay to clock signal, meanwhile, postpone control logic module 34 according to synchronous logic moduleIn 33, the stable output signal of the n level d type flip flop of output generates true random number output.
Right by generating control signal adjustment adjustable delay module 32 in delay control logic module 34The time delay of the first clock signal, this is in order to make the first clock signal in process adjustable delay moduleWhen each delay cell in 32, there is delay, thus obtain n level d type flip flop D input and timeThe relativeness of the rising edge of the clock signal of Zhong Duan as shown in Figure 5, is the utility model random numberThe 3rd clock signal of the D input of n level d type flip flop in Fig. 4 example of generating apparatus embodimentThe relativeness of the rising edge of the second clock signal of rising edge and clock end, D is defeated for n level d type flip flopEnter the rising edge that end experiences the 3rd clock signal simultaneously, n level d type flip flop clock end experiences second successivelyThe rising edge of clock signal, the time of d type flip flop clock end experience second clock signal rising edges at different levelsDiffer the first scheduled time Δ T. Postponing, control logic module 34 is defeated according to synchronous logic module 33The stable output signal of the n level d type flip flop going out generates control signal, finally reaches the 1st grade of D and triggersThe output of device and n level d type flip flop is normal, the output generation metastable state of intergrade d type flip flop thisStable state, the clock end of the 1st grade of d type flip flop experiences the rising edge of second clock signal the earliest, theThe clock end of n level d type flip flop experiences the rising edge of second clock signal the latest.
Control the time delay of adjustable delay module 32 by postponing control logic module 34, Ke YibaoCard obtains the D input of n level d type flip flop and the relativeness on clock end clock variation edge of expection,The metastable state phenomenon that ensures intergrade d type flip flop output occurs, thereby has ensured the very random of outputThe randomness of number.
In the example shown in Fig. 4, delay control logic module 34 generates the specific works of control signalPrinciple is: according to the stable output of n level d type flip flop, according to the output letter of the 1st grade of d type flip flopNumber and the output signal of n level d type flip flop judge and generate corresponding control signal, corresponding closingBe as shown in table 1 below:
Table 1
Known according to the corresponding relation in table 1, in n level d type flip flop, correctly sample D as long as makeThe rising edge of input the 3rd clock signal, just can ensure the defeated of trigger in intergrade d type flip flopGo out to have metastable state phenomenon to occur, then in delay control logic module 34, pass through centre D at different levelsCombinatorial operation is carried out in the output of trigger, generates true random number output. The combinatorial operation is here concreteCan be the output of each trigger to be carried out to the logical operations such as XOR, can also be to the output of each triggerCarry out Hash computing etc.
As shown in Figure 6, for the second exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, is with the difference of the first example, in this example, has increased a reverser 61,Reverser 61 be input as the first clock signal, the output of reverser 61 and the D of d type flip flops at different levelsInput connects, so in this example, the 3rd clock signal is for to carry out nothing to the first clock signalThe clock signal obtaining after the non-processing of delay logic, so the D input of n level d type flip flop is to declineThe 3rd clock signal on edge is as input, and adopts second clock letter at the clock end of n level d type flip flopNumber rising edge as judgement, therefore, as shown in Figure 7, be the utility model random number generating apparatusIn Fig. 6 example of embodiment the trailing edge of the 3rd clock signal of the D input of n level d type flip flop withThe relativeness of the rising edge of the second clock signal of clock end, n level d type flip flop D input simultaneouslyExperience the trailing edge of the 3rd clock signal, n level d type flip flop clock end experiences second clock signal successivelyRising edge, the time phase difference first of n level d type flip flop clock end experience second clock signal rising edgeScheduled time Δ T.
Alternatively, in the present embodiment, n second clock signal is as the input of n level memory cellSignal, the 3rd clock signal is as the clock signal of n level memory cell, in adjustable delay module 32N delay cell connects respectively the input of n level memory cell, by postponing control logic module 34The transmission delay of output control signal control adjustable delay module 32, like this, each the 3rd clock signalClock along the clock end that can be added in n level memory cell simultaneously, but the input of every one-level memory cellThe clock of end experience changes along postponing for first scheduled time than upper level memory cell, thereby makes everyThe input of one-level memory cell changes along having relative relation with the clock of clock end.
As shown in Figure 8, for the 3rd exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, is with the difference of the first example, in this example, and the n in adjustable delay module 32The output of level delay cell is connected with the D input of n level d type flip flop respectively. With the first example class seemingly,Can obtain, as shown in Figure 9, be Fig. 8 example of the utility model random number generating apparatus embodimentThe 3rd clock of the rising edge of the second clock signal of the D input of middle n level d type flip flop and clock endThe relativeness of the rising edge of signal, n level d type flip flop clock end experiences the 3rd clock signal simultaneouslyRising edge, n level d type flip flop D input experiences the rising edge of second clock signal, D at different levels successivelyFirst scheduled time of the time phase difference Δ T of trigger D input experience second clock signal rising edge,Reaching after stable state, the D input of the 1st grade of d type flip flop experiences second clock signal the earliestRising edge, the D input of n level d type flip flop experiences the rising edge of second clock signal the latest.
Similarly, delay control logic module 34 generates the specific works principle of control signal: according to nThe stable output of level d type flip flop, according to the output signal of the 1st grade of d type flip flop and n level DThe output signal of trigger judges and generates corresponding control signal, and corresponding relation is as 2 of following tablesShow:
Table 2
Known according to the corresponding relation in table 2, in n level d type flip flop, correctly sample D as long as makeThe rising edge of input second clock signal, just can ensure the defeated of trigger in intergrade d type flip flopGo out to have metastable state phenomenon to occur.
Alternatively, in this example, can with the example shown in Fig. 6 in similar, increase by one anti-To device 61, be connected between the clock end of the first clock signal and d type flip flops at different levels, so D at different levelsThe clock signal of trigger clock end is for to carry out without obtaining after the non-processing of delay logic the first clock signalThe 3rd clock signal, like this, the D input of n level d type flip flop is the second clock letter of rising edgeNumber as input signal, but be the decline that adopts the 3rd clock signal at the clock end of n level d type flip flopAlong conduct judgement, n level d type flip flop D clock end experiences the trailing edge of the 3rd clock signal simultaneously,The D input of n level d type flip flop experiences the rising edge of second clock signal successively, n level d type flip flopFirst scheduled time of the time phase difference Δ T of D input experience second clock signal rising edge.
As shown in figure 10, for the 4th exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, is with the difference of the first example, in this example, n level d type flip flop is trailing edgeTrigger, thus the detailed process all fours in specific works process and first example of this example,Just the variation of clock signal, along becoming trailing edge from rising edge, does not repeat them here. Similarly, canTo obtain the relative pass of the D input of n level d type flip flop and the trailing edge of the clock signal of clock endSystem as shown in figure 11, is n in Figure 10 example of the utility model random number generating apparatus embodimentThe trailing edge of the 3rd clock signal and the second clock signal of clock end of the D input of level d type flip flopThe relativeness of trailing edge, n level d type flip flop D input experience simultaneously the 3rd clock signal underFall edge, n level d type flip flop clock end experiences the trailing edge of second clock signal successively, and D at different levels triggerFirst scheduled time of the time phase difference Δ T of device clock end experience second clock signal trailing edge. ReachingThe output of the 1st grade of d type flip flop and n level d type flip flop is normal, the output of intergrade d type flip flopOccur after this stable state of metastable state, the clock end of the 1st grade of d type flip flop experiences second clock the earliestThe trailing edge of signal, the clock end of n level d type flip flop experiences the trailing edge of second clock signal the latest.
In this example, postponing control logic module 34 is believing according to the output of the 1st grade of d type flip flopNumber and the output signal of n level d type flip flop judge and generate in corresponding control signal processCorresponding relation is as shown in table 3 below:
Table 3
Known according to the corresponding relation in table 3, in n level d type flip flop, correctly sample D as long as makeThe trailing edge of input the 3rd clock signal, just can ensure the defeated of trigger in intergrade d type flip flopGo out to have metastable state phenomenon to occur.
As shown in figure 12, for the 5th exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, is with the difference of the 4th example, in this example, has increased a reverser 61,Reverser 61 be input as the first clock signal, the output of reverser 61 and the D of d type flip flops at different levelsInput connects, so in this example, the 3rd clock signal is for to carry out nothing to the first clock signalThe clock signal obtaining after the non-processing of delay logic, so the D input of n level d type flip flop is to riseThe 3rd clock signal on edge is as input, and adopts second clock letter at the clock end of n level d type flip flopNumber trailing edge as judgement, therefore, as shown in figure 13, be the utility model random number generating apparatusThe rising edge of the 3rd clock signal of the D input of n level d type flip flop in Figure 12 example of embodimentWith the relativeness of the trailing edge of the second clock signal of clock end, n level d type flip flop D input withThe rising edge of Shi Jingli the 3rd clock signal, n level d type flip flop clock end experiences second clock letter successivelyNumber trailing edge, the time phase difference of n level d type flip flop clock end experience second clock signal trailing edge theOne scheduled time Δ T.
As shown in figure 14, for the 6th exemplary construction of the utility model random number generating apparatus embodiment is shownIntention, is with the difference of the 4th example, in this example, and the n in adjustable delay module 32The output of level delay cell is connected with the D input of n level d type flip flop respectively, this situation and Fig. 8The 3rd shown example class seemingly, difference be exactly in Fig. 8 example n level d type flip flop adopt be rising edgeTrigger, what in this example, n level d type flip flop adopted is trailing edge trigger, specific works process existsThis repeats no more. As shown in figure 15, be Figure 14 of the utility model random number generating apparatus embodimentIn example the 3rd of the trailing edge of the second clock signal of the D input of n level d type flip flop and clock end theThe relativeness of the trailing edge of clock signal, n level d type flip flop clock end experiences the 3rd clock letter simultaneouslyNumber trailing edge, n level d type flip flop D input experiences the trailing edge of second clock signal, n successivelyFirst scheduled time of the time phase difference Δ of level d type flip flop D input experience second clock signal trailing edgeT。
Alternatively, in this example, can also with the example shown in Figure 12 in similar, increase by oneReverser 61, is connected between the clock end of the first clock signal and d type flip flops at different levels, so at different levelsThe clock signal of d type flip flop clock end is for carrying out the first clock signal without obtaining after the non-processing of delay logicThe 3rd clock signal arriving, like this, the D input of n level d type flip flop is the second clock of trailing edgeSignal, as input, is to adopt the rising edge of the 3rd clock signal to do at the clock end of n level d type flip flopFor judgement, n level d type flip flop D clock end experiences the rising edge of the 3rd clock signal, n level simultaneouslyThe D input of d type flip flop experiences the trailing edge of second clock signal successively, the D of n level d type flip flopFirst scheduled time of the time phase difference Δ T of input experience second clock signal trailing edge.
As shown in figure 16, for adopting 5 grades of D to touch in the utility model random number generating apparatus embodimentThe circuit timing diagram of the example of hair device, the structure in the example of this example shown in can corresponding diagram 4, institute5 grades of d type flip flops that adopt are rising edge trigger, therefore, in this example, according to input signalSequential chart, according to the situation of the rising edge of clock end experience second clock signal and Ts, ThTime relationship, for the 1st grade of d type flip flop, input signal does not change in Ts+Th time window,So there is not metastable state in the 1st grade of d type flip flop output, the 1st grade of d type flip flop output low level;The Th of the 2nd grade of d type flip flop is negative value, can not meet the retention time of d type flip flop, so the 2ndLikely there is metastable state in the output of level d type flip flop; The Th of 3rd level d type flip flop is similarly negativeValue, Ts and Th all can not meet Time Created and the retention time of d type flip flop, so 3rd level DLikely there is metastable state in the output of trigger; The Ts time of the 4th grade of d type flip flop is too short, noCan meet the Time Created of d type flip flop, so Asia likely occurs the output of the 4th grade of d type flip flopStable state; The Ts of the 5th grade of d type flip flop and Th all meet Time Created and the retention time of d type flip flop,So there is not metastable state in the 5th grade of d type flip flop output, the 5th grade of d type flip flop output high level.So in this example, the 1st grade of d type flip flop output low level, the 5th grade of d type flip flop are exported highLevel, shows D input defeated of d type flip flop during the clock sampling of these 5 d type flip flopsEnter signal and have a rising edge, this is just consistent with the analysis in aforesaid table 1. In addition, due inBetween the output of 3 grades of d type flip flops may there is metastable state, can ensure to obtain the randomness of true random number.
Finally it should be noted that: above embodiment only in order to the technical solution of the utility model to be described but notRestriction, although the utility model is had been described in detail with reference to preferred embodiment, this area commonTechnical staff should be appreciated that and can modify or be equal to replacement the technical solution of the utility model,And do not depart from the spirit and scope of technical solutions of the utility model.
Claims (5)
1. a random number generating apparatus, is characterized in that, comprising:
Adjustable delay module, for the first clock signal is postponed, generates n second clock letterNumber, under the control of control signal, the delay of described n second clock signal is adjusted, wherein,Described n second clock signal increases successively with respect to the delay of described the first clock signal, and n is largeIn or equal 3 natural number;
Memory module, comprises n level memory cell, and described n level memory cell comprises that the 1st grade of storage is singleUnit, intergrade memory cell and n level memory cell, described n second clock signal and the 3rd o'clockClock signal, respectively as input signal and the clock signal of described n level memory cell, makes the described the 1stLevel memory cell and described n level memory cell are output as normal condition, and described intergrade storage is singleIn unit, have at least one-level memory cell to be output as metastable state, described the first clock signal and the described the 3rdClock signal is synchronizing signal;
Synchronous logic module, for the output of described n level memory cell is carried out synchronously, to obtainThe stable output of described n level memory cell, eliminates described metastable state;
Postpone control logic module, for according to the stable output of described n level memory cell, generateDescribed control signal, generates and exports true random number.
2. device according to claim 1, is characterized in that, described n second clock signalWith described the first clock signal respectively as input signal and the clock signal tool of described n level memory cellBody is:
Described n second clock signal is as the input signal of described n level memory cell, the described the 3rdClock signal is as the clock signal of described n level memory cell; Or
Described n second clock signal is as the clock signal of described n level memory cell, the described the 3rdClock signal is as the input signal of described n level memory cell.
3. device according to claim 1, is characterized in that, described delay control logic moduleFor stablizing according to the stable output of described the 1st grade of memory cell and described n level memory cellOutput, generate described control signal; Wherein, when the stable output of described the 1st grade of memory cellWith the stable output of described n level memory cell be not expect clock change along time, generate representIncrease or reduce the control signal postponing.
4. device according to claim 1, is characterized in that, described adjustable delay module comprisesThe n a being connected in series delay cell, 1 second clock signal of each delay cell output, described nThe delay of the 1st delay cell in individual delay cell is adjusted under the control of described control signalWhole.
5. device according to claim 1 and 2, is characterized in that, described the first clock signalWith described the 3rd clock signal be same clock signal; Or described the 3rd clock signal is for to instituteState the first clock signal and carry out the clock signal obtaining without after delay logic processing.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105242903A (en) * | 2015-10-21 | 2016-01-13 | 昆腾微电子股份有限公司 | Random number generation device and method |
| CN112910451A (en) * | 2021-01-18 | 2021-06-04 | 北京中科芯蕊科技有限公司 | Asynchronous traveling wave state machine |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105242903A (en) * | 2015-10-21 | 2016-01-13 | 昆腾微电子股份有限公司 | Random number generation device and method |
| CN105242903B (en) * | 2015-10-21 | 2018-01-16 | 昆腾微电子股份有限公司 | Generating random number apparatus and method |
| CN112910451A (en) * | 2021-01-18 | 2021-06-04 | 北京中科芯蕊科技有限公司 | Asynchronous traveling wave state machine |
| CN112910451B (en) * | 2021-01-18 | 2023-07-14 | 北京中科芯蕊科技有限公司 | Asynchronous traveling wave state machine |
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