CN102081426A - Frequency adjustment device and frequency adjustment method for adjustable oscillator - Google Patents
Frequency adjustment device and frequency adjustment method for adjustable oscillator Download PDFInfo
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- CN102081426A CN102081426A CN200910222682XA CN200910222682A CN102081426A CN 102081426 A CN102081426 A CN 102081426A CN 200910222682X A CN200910222682X A CN 200910222682XA CN 200910222682 A CN200910222682 A CN 200910222682A CN 102081426 A CN102081426 A CN 102081426A
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Abstract
The invention relates to a frequency adjustment method for an adjustable oscillator. The method comprises the following steps of: counting the oversampling number of an oversampling signal, and estimating the accumulated bit number of universal serial bus (USB) data stream according to the oversampling signal; when the accumulated bit number is more than or equal to a preset value, calculating the difference of the oversampling number and M times the accumulated bit number; and determining the frequency adjustment lattice number of the oversampling signal according to the difference. In addition, the invention provides a frequency adjustment device for the adjustable oscillator. By the frequency adjustment device and the frequency adjustment method, an accurate oscillating element is not required to be hung, and the oscillating frequency of the adjustable oscillator can be automatically and instantaneously adjusted according to any type of data packet in the received USB data stream.
Description
Technical field
The present invention relates to a kind of data transmission structure and method, and relate in particular to a kind of frequency adjusting device and frequency adjusting method of adjusting the oscillation frequency of adjustable oscillator according to data stream automatically.
Background technology
Use the oscillatory circuit of outside sequential can be in order to clock signal to be provided, and this oscillatory circuit uses plug-in accurate sequential element usually, for example crystal oscillator (crystal resonator) or ceramic resonator (ceramic resonator) provide reference frequency to this oscillatory circuit.Yet, use plug-in accurate sequential element not only can increase system cost, and one or two pin (pin) also must be set in addition with as the interface of communicating by letter on the control chip of oscillatory circuit with this accurate sequential element.
Control chip for example also can utilize phase-locked loop (PLL) or delay phase-locked loop road (DLL) internal frequency to be adjusted to consistent with the data transfer rate (data rate) of the data stream that is received except can using the plug-in reference frequency that accurate sequential element provided; Yet the method need spend the long adjustment time usually, thereby and be not suitable for some application, for example on the USB device.
In view of this, be necessary to propose a kind ofly need not use the plug-in accurate sequential element still can be fast and adjust the frequency adjusting device and the frequency adjusting method of the oscillation frequency of adjustable oscillator automatically, to solve existing problem in the prior art.
Summary of the invention
The objective of the invention is to propose a kind of frequency adjusting device and frequency adjusting method that need not use the adjustable oscillator of plug-in oscillator, it can adjust the oscillation frequency of adjustable oscillator automatically according to the packet of any type in the usb data stream that is received.
The objective of the invention is to propose a kind of frequency adjusting device and frequency adjusting method of adjustable oscillator, it can immediately adjust the oscillation frequency of adjustable oscillator during data transmission, cause frequency drift to avoid adjustable oscillator because of environmental change.
The present invention proposes a kind of frequency adjusting method of adjustable oscillator, and this method comprises the following steps: to receive usb data stream and clock signal; Estimate the accumulative total bit number that usb data flows according to this clock signal, and the over-sampling number of clock signal is counted; When this adds up bit number more than or equal to preset value, compare the doubly described accumulative total of over-sampling number and M bit number; When having served as hits, reduce the frequency of clock signal greater than the doubly described accumulative total of M bit number; And when having served as hits, promote the frequency of clock signal less than the doubly described accumulative total of M bit number.
The present invention proposes a kind of frequency adjusting method of adjustable oscillator in addition, in order to adjust the oversampled signals that adjustable oscillator sends according to usb data stream.This frequency adjusting method comprises the following steps: the over-sampling number of oversampled signals is counted, and estimates the accumulative total bit number of usb data stream according to oversampled signals; When this adds up bit number more than or equal to preset value, calculate the difference of the doubly described accumulative total of over-sampling number and M bit number; And the frequency adjustment lattice number that determines oversampled signals according to this difference.
The present invention proposes a kind of frequency adjusting device of adjustable oscillator in addition, in order to adjust the oscillation frequency of adjustable oscillator according to usb data stream.This frequency adjusting device comprises counting processing unit and controller.Described counting processing unit is counted the vibration number of adjustable oscillator, and according to the accumulative total bit number of this vibration number estimation usb data stream, and relatively M doubly is somebody's turn to do accumulative total bit number and vibration number, adjusts the lattice number with output frequency.Described controller is coupled between counting processing unit and the adjustable oscillator, adjusts the oscillation frequency that the lattice number is adjusted described adjustable oscillator according to described frequency.
In the frequency adjusting device and frequency adjusting method of adjustable oscillator of the present invention, utilize the packet (data packet) of any type of USB (universal serial bus) (USB), for example, but be not limited to, set in grouping (SETUP packet), packet (DATA packet) and the output grouping (OUT packet), finish the foundation that the bit between (EOP) bit is adjusted as frequency between idle (Idle) bit and grouping, so need not use plug-in accurate sequential element among the present invention.Frequency adjusting device of the present invention and frequency adjusting method are applicable to the device that uses USB (universal serial bus), for example USB mouse.
Description of drawings
Fig. 1 has shown the calcspar of the self-adjustable oscillatory circuit of an embodiment of the present invention;
Fig. 2 a has shown the partial data stream that usb host is exported;
Fig. 2 b has shown the graph of a relation of the data stream of the oversampled signals of USB device and Fig. 2 a;
Fig. 3 has shown maximum jitter budget required in the low speed transmissions;
Fig. 4 has shown the pairing bit number of over-sampling number between the adjacent transform strike slip boundary of usb data stream among the present invention;
Fig. 5 has shown the synoptic diagram of frequency adjusting method of the adjustable oscillator of the embodiment of the invention;
Fig. 6 has shown the process flow diagram of frequency adjusting method of the adjustable oscillator of an embodiment of the present invention;
Fig. 7 has shown the process flow diagram of frequency adjusting method of the adjustable oscillator of the another kind of embodiment of the present invention; And
Fig. 8 has shown through the maximum frequency error after the frequency adjusting method adjustment once of the present invention.
The main element symbol description
1 self-adjustable oscillatory circuit, 101 input ends
102 output terminals, 103 feedback input ends
104 control output ends, 11 frequency adjusting devices
111 counting processing units, 112 controllers
12 adjustable oscillator S
1Control signal
S
2Frequency is adjusted lattice and is counted Data USB data stream
CLK clock signal between the CI count block
Embodiment
For allow above-mentioned and other purposes of the present invention, feature and advantage can be more obvious, hereinafter will cooperate appended diagram, be described in detail below.In addition, in explanation of the present invention, identical member is with identical symbolic representation, in this close chat earlier bright.
According to universal serial bus specification (Universal Serial Bus Specification, version 1.1) contained, the data transfer rate error of low speed USB device must can correctly operate in ± 1.5%, the data transfer rate error of including usb host simultaneously in is that the error of the built-in oscillator of ± 0.25%, one low speed USB device must be maintained at ± can guarantee in 1.25% USB interface and correctly carries out data transmission.Therefore, if the over-sampling frequency of hypothesis USB device is 24MHz (16 times of over-sampling ratio), then the oscillation frequency of the built-in oscillator of this USB device must be in the scope of 24MHz ± 300KHz.It must be understood that the over-sampling frequency of USB device is not defined as 24MHz.
Please refer to shown in Figure 1ly, it has shown the self-adjustable oscillatory circuit 1 of an embodiment of the present invention, and it has input end 101 and output terminal 102.This self-adjustable oscillatory circuit 1 can be built in the USB device, and USB mouse (mouse) for example with as its local oscillator, and produces clock signal with adjustable frequency CLK according to usb data stream Data.This clock signal clk for example recovers the oversampled signals (oversampling signal) of (datarecovery) for being used for data.
Described input end 101 is in order to receive data stream (data stream) Data from usb host, and described output terminal 102 is in order to clock signal CLK.Error between the data transfer rate of the frequency of this clock signal clk and data stream Data (data rate) for example can be adjusted to data stream Data M haplotype data rate 0.805%～1.027% between, wherein M is the positive integer of representative over-sampling than (oversampling ratio).Data stream Data for example is any type of packet in the usb data stream, for example sets the grouping of grouping (SETUP packet), output grouping (OUT packet), packet (DATA packet) or other types.Among a kind of embodiment, described data stream Data for example can be low speed (lowspeed) data stream, and its data transfer rate is 1.5MHz.
Described self-adjustable oscillatory circuit 1 comprises frequency adjusting device 11 and the adjustable oscillator 12 that couples mutually.This adjustable oscillator 12 for example can be RC oscillator or other suitable adjustable oscillators.Described frequency adjusting device 11 flows Data from the usb data that input end 101 receives from usb host.Described frequency adjusting device 11 comprises feedback input end 103 and control output end 104.Frequency adjusting device 11 self-feedback input ends 103 receive the clock signal clk of feedback from adjustable oscillator 12, and control output terminal 104 output control signal S certainly
1To adjustable oscillator 12, wherein control signal S
1For example can be the digital controlled signal that comprises a plurality of bits.Adjustable oscillator 12 is according to control signal S
1Clock signal CLK is with the reference frequency as the USB device.
Please be simultaneously with reference to shown in Fig. 2 a and Fig. 2 b, Fig. 2 a has shown that usb host (USB host) is sent to the synoptic diagram of the packet of USB device (USB device), comprise one herein and set a grouping (SETUP packet) and an output grouping (OUTPUT packet), but in fact also may comprise the packet of other any types.Fig. 2 b has shown the relation of part enlarged drawing and 24MHz over-sampling frequency and the 1.5MHz data stream Data of Fig. 2 a, that is among this embodiment, the built-in oscillator of USB device will be obtained 16 oversampled points between each bit period of a data grouping under situation accurately.
Please be simultaneously with reference to shown in Fig. 1, Fig. 2 a and Fig. 2 b, counting processing unit 111 CI between a count block counts the over-sampling number between the clock signal clk of bit number between first bit of (SYNC) bit synchronously and the previous bit of grouping end (EOP) bit and feedback in the packet of any type of data stream Data simultaneously, and relation more between the two, adjust lattice with the frequency that determines adjustable oscillator 12 and count S
2112 of controllers are adjusted lattice according to frequency and are counted S
2Carry out the oscillation frequency adjustment of adjustable oscillator 12; Wherein, if CI comprises N bit at least between a count block, when first packet among the CI between this count block (for example set grouping) from synchronization bit to the previous bit of the end bit of dividing into groups during (bit number of SYNC+PID+ADDR+ENDP+CRC5 as Fig. 2 a) not enough N bit, then when receiving the grouping end bit, stop counting, and when first bit of the synchronization bit that receives next packet once again (as the grouping of the output among Fig. 2 a), begin counting once again, when counting, stop extremely greater than N bit.
Because there is shake (jitter) in data stream Data when transmission, so the bit number that CI comprised between each count block must be able to be allowed the jitter budget (jitter budget) under the poorest condition (worst-case).Please refer to shown in Figure 3ly, it has shown data stream through the hub (HUB) of 5 serial connections and transmit continuous 1 situation, and with regard to the USB normalized definition, continuous six 1 can be inserted one 0, and promptly so-called bit is filled (Bit stuffing), is the poorest condition this moment.As we know from the figure, have the maximum time shake when changing (paired transition) in pairs, it is 184ns.In low speed transmissions, if will shake time and data transfer rate permission (184/666.66 * 1.25%=22.08 bit) maximum time divided by each bit among the data stream Data, can obtain when low speed transmissions that CI is minimum between a count block must comprise 23 bits, can avoid taking place the situation of miscount.The detailed content of Fig. 3 is recorded in universal serial bus specification the 1.1st edition.
Among the present invention, the mode of the bit number of estimation data stream Data is to be undertaken by the bit number of estimating the bit number between the adjacent transform strike slip boundary (transition edge) and add up between the continuous adjacent transform strike slip boundary among the CI between a count block.Because packet is adopted the non-return-to-zero reversal phase coding (it may be included 6 continuous 1 at most for Non return to zero, coded system NRZI) in the USB (universal serial bus).When continuous bit 1 appears in data stream Data, during continuous 1, transform strike slip boundary can not occur, so the present invention need carry out the bit number estimation at the data of successive bits 1.
Please be simultaneously with reference to Fig. 2 a, Fig. 2 b and shown in Figure 4, Fig. 4 has shown the pairing bit number of over-sampling number between the adjacent transform strike slip boundary of usb data stream among the present invention.When the frequency error that dispatches from the factory of adjustable oscillator 12 is adjusted to when being lower than 3%, counting processing unit 111 can be estimated bit number between the adjacent transform strike slip boundary according to the setting of Fig. 4 according to the bit number among the clock signal clk estimation data stream Data time.As shown in Figure 4, when the over-sampling number between two adjacent continuous transform strike slip boundaries was lower than 24,111 judgements of counting processing unit only comprised 1 bit; When the over-sampling number between two continuous transform strike slip boundaries was between 24 and 40,111 judgements of counting processing unit comprised 2 bits; ...; When the over-sampling number between two continuous transform strike slip boundaries during greater than 104,111 judgements of counting processing unit comprise 7 bits, and this moment, data stream was 6 continuous 1 and 10.By this, 111 of processing units of counting can according among the data stream Data between the adjacent transform strike slip boundary pairing over-sampling number estimate bit number between the two adjacent transform strike slip boundaries, and the bit number of continuous adjacent transform strike slip boundary added up, to obtain the accumulative total bit number.
Please be simultaneously with reference to Fig. 1, Fig. 2 a, Fig. 2 b and shown in Figure 5, Fig. 5 has shown the synoptic diagram of frequency adjusting method of the adjustable oscillator of the embodiment of the invention.Counting processing unit 111 is adjusted the oscillation frequency of the clock signal clk that adjustable oscillator 12 produced according to the usb data that received stream Data and clock signal clk.
Step S
210: counting processing unit 111 receives usb data stream and clock signal, over-sampling number to this clock signal clk is counted, and, wherein estimate the data type (pattern) that this accumulative total bit number and data stream Data comprise and have nothing to do according to the accumulative total bit number among the over-sampling number of the clock signal clk estimation data stream Data.Counting processing unit 111 is estimated the bit number between the adjacent transform strike slip boundary according to pairing over-sampling number between the two adjacent transform strike slip boundaries among Fig. 4, and the bit number between the accumulative total continuous adjacent transform strike slip boundary, to obtain the accumulative total bit number.
Step S
220: whether counting processing unit 111 judges the accumulative total bit numbers greater than preset value, wherein according to Fig. 3 as can be known this preset value be at least 23.When adding up bit number, then enter step S greater than preset value
230
Step S
230: counting processing unit 111 judges whether the over-sampling number doubly adds up bit number greater than M, wherein M is for being dividend with the expectation oscillation frequency of adjustable oscillator 12 or the system frequency of USB device, and be the merchant of divisor with the data transfer rate of data stream Data, that is over-sampling is than (oversamplingratio).For example among Fig. 2 b, M is 16.When having served as hits and doubly having added up bit number greater than M, execution in step S then
240～S
243, to reduce the oscillation frequency of clock signal clk; When having served as hits and doubly having added up bit number less than M, execution in step S then
250～S
253, to promote the oscillation frequency of clock signal clk.
Step S
240: when having served as hits and doubly adding up bit number, the over-sampling number is deducted M doubly add up bit number in the hope of first difference greater than M.
Step S
241: counting processing unit 111 is tried to achieve and is reduced the lattice number, and is sent to controller 112, wherein reduces lattice number=(first difference/M doubly adds up bit number)/(frequency is adjusted the M haplotype data rate of resolution/data stream).One is reduced the lattice numerical example as being the frequency adjustment resolution (resolution) of adjustable oscillator 12.For example in low speed transmissions, M can be 16, and the M haplotype data rate of data stream can be 24MHz, but the present invention is not limited to this.
Step S
242: counting processing unit 111 judges that whether reduction lattice number is less than 1; If, execution in step S then
260If not, execution in step S then
243
Step S
243: judge when counting processing unit 111 and to reduce the lattice numbers greater than 1 the time, then transmit these reduction lattice and count S
2To controller 112.112 of this controllers send control signal S according to this
1Reduce the oscillation frequency of adjustable oscillator 12.Simultaneously, 111 of processing units of counting are again by step S
210Beginning adjustment next time.Among a kind of embodiment, each reduces lattice number can be between 110KHz～140KHz, but is not limited to this.Among a kind of embodiment, when the reduction lattice number of being obtained not when the positive integer, can use rounding-off method or directly fraction part is removed so that this reduction lattice number becomes positive integer.
Step S
260: judge when counting processing unit 111 and to reduce the lattice numbers less than 1 the time, represent that then the oscillation frequency of adjustable oscillator 12 is stable and do not adjust.Then, counting processing unit 111 is begun again the over-sampling number of clock signal clk to be counted by the next bit of CI between the count block of finishing counting, the accumulative total bit number of estimation usb data stream, and from step S
210Carry out correction next time; Be understandable that, if between the count block last bit of CI just be CRC5 (during with reference to a) last bit of Fig. 2, between next count block then from first bit of the SYNC of next packet.
Step S
250: when having served as hits and doubly adding up bit number, M is doubly added up bit number deduct the over-sampling number in the hope of second difference less than M.
Step S
251: counting processing unit 111 is tried to achieve the The Upgrade Lattice number, and is sent to controller 112, wherein The Upgrade Lattice number=(second difference/M doubly adds up bit number)/(frequency is adjusted the M haplotype data rate of resolution/data stream).A The Upgrade Lattice numerical example is as being the frequency adjustment resolution of adjustable oscillator 12.
Step S
252: counting processing unit 111 judges that whether the The Upgrade Lattice number is less than 1; If, execution in step S then
260If not, execution in step S then
253
Step S
253: when counting processing unit 111 judges that the The Upgrade Lattice numbers greater than 1 the time, then transmit The Upgrade Lattice and count S
2To controller 112.112 of controllers send control signal S according to this
1, promote the oscillation frequency of adjustable oscillator 12.Simultaneously, 111 of processing units of counting are again by step S
210Beginning adjustment next time.Among a kind of embodiment, each The Upgrade Lattice number can be between 110KHz～140KHz, but is not limited to this.Among a kind of embodiment, when the The Upgrade Lattice number of being obtained not when the positive integer, can use rounding-off method or directly fraction part is removed so that this The Upgrade Lattice number becomes positive integer.
Therefore, the frequency adjusting method of the adjustable oscillator of an embodiment of the present invention comprises the following steps: to receive usb data stream and clock signal (step S as shown in Figure 6
310); Estimate the accumulative total bit number that usb data flows according to this clock signal, and the over-sampling number of clock signal is counted (step S
320); When adding up bit number greater than preset value, relatively over-sampling number and M doubly add up bit number (step S
330); When having served as hits and doubly adding up bit number, reduce frequency (the step S of clock signal greater than M
340); And when having served as hits and doubly adding up bit number, promote frequency (the step S of clock signal less than M
350).The detailed embodiment of present embodiment has been illustrated in Fig. 5 and the related description thereof, so repeat no more in this.
The frequency adjusting method of the adjustable oscillator of the another kind of embodiment of the present invention as shown in Figure 7, this frequency adjusting method is adjusted the oversampled signals that adjustable oscillator sends in order to according to usb data stream.This frequency adjusting method comprises the following steps: the over-sampling number of oversampled signals is counted, and estimates accumulative total bit number (the step S of usb data stream according to oversampled signals
410); When this adds up bit number greater than preset value, calculate difference (the step S that over-sampling number and M doubly add up bit number
420); And frequency adjustment lattice number (the step S that determines oversampled signals according to this difference
430).
Please refer to shown in Figure 8ly, it has shown through after frequency adjusting device of the present invention and the method adjustment once, the maximum error of adjustable oscillator 12; Wherein, when initial error was between 1%～3%, the error after adjustment once of the present invention can be between 0.805%～1.027%.Among Fig. 8, CI is grouped into example (totally 64 bits) with two inputs that comprise 32 bits between the count block, the system frequency of low speed USB device (being the oscillation frequency of adjustable oscillator 12) is assumed to be 24MHz (the over-sampling cycle was 41.667 nanoseconds), that is 16 times of over-sampling ratios.In the frequency adjusting device and method of adjustable oscillator of the present invention, the initial error of adjustable oscillator 12 (initial error) preferably is adjusted into and is lower than 3%, so that counting processing unit 111 can be estimated correct bit number between the adjacent transform strike slip boundary according to Fig. 4.In addition, in the present embodiment, the frequency of adjustable oscillator 12 is adjusted the resolution hypothesis between 110KHz～140KHz, but the present invention is not limited to this.
The initial error of adjustable oscillator 12 is 1%～3%, and it is shown in first row of Fig. 8.Be the account form of first row of example key diagram 8 now, and the account form of other each row is all identical, so repeat no more with initial error 1%.In the secondary series, the desirable bit time of 64 bits is 64 * (1/1.5MHz)=42667 nanoseconds (ns).
In the 3rd row, the shortest time of 64 bits is desirable bit time-maximum jitter time, i.e. 42667-184=42483 nanosecond when considering shake; Wherein, the maximum jitter time please refer to Fig. 3.
In the 4th row, the maximum duration of 64 bits is desirable bit time+maximum jitter time, i.e. 42667+184=42851 nanosecond when considering shake.
The 5th classifies between the count block minimum over-sampling number among the CI as, equals (bit shortest time * (1-initial error)/over-sampling cycle)-sampling error; Each packet of hypothesis has the sampling error of 1 bit in the present embodiment, and therefore the sampling error of 2 input groupings is 2.Minimum over-sampling number=42483 * (1-1%)/41.667)-2=1007.
The 6th classifies between the count block maximum over-sampling number among the CI as, equals (bit maximum duration * (1+ initial error)/over-sampling cycle)+sampling error, promptly equals 42851 * (1+1%)/41.667ns)+2=1041.
The 7th row and the 8th row are respectively the minimum value and the maximal value of clock minimum zone, wherein minimum value=(minimum over-sampling number-1) * 1000/ bit maximum duration, i.e. (1007-1) * 1000/42851=23.477MHz; Maximal value=(minimum over-sampling number-1) * 1000/ bit shortest time, i.e. (1007-1) * 1000/42483=23.680MHz.
The 9th row and the tenth row are respectively the minimum value and the maximal value of clock maximum magnitude, wherein minimum value=(maximum over-sampling number-1) * 1000/ bit maximum duration, i.e. (1041-1) * 1000/42851=24.270MHz; Maximal value=(maximum over-sampling number-1) * 1000/ bit shortest time, i.e. (1041-1) * 1000/42483=24.480MHz.
The 11 classifies the The Upgrade Lattice number with respect to different initial errors as.
The 12 row and 13 row are respectively minimum frequency and the maximum frequency that promotes the back oscillation frequency.The minimum value of minimum frequency=clock minimum zone+The Upgrade Lattice number * minimum resolution is 23.477MHz+3 * 110KHz=23.807MHz; The maximal value of maximum frequency=clock minimum zone+The Upgrade Lattice number * maximum resolution is 23.680MHz+3 * 140KHz=24.100MHz.
The 14 classifies the reduction lattice number with respect to different initial errors as.
The 15 row and 16 row are respectively minimum frequency and the maximum frequency that reduces the back oscillation frequency.The minimum value of minimum frequency=clock maximum magnitude-reduction lattice number * maximum resolution is 24.270MHz-3 * 140KHz=23.850MHz; The maximal value of maximum frequency=clock maximum magnitude-reduction lattice number * minimum resolution is 24.480MHz-3 * 110KHz=24.150MHz.
The 17 classifies the maximum error of adjusting the back oscillation frequency as, and maximum error betides the minimum frequency that promotes the back frequency herein, so maximum error is 100% * (24-23.807)/24=0.805%.
Be understandable that though describe with low speed transmissions among the present invention, it only is exemplary; Frequency adjusting device of the present invention and method are not limited to low speed USB device.
As previously mentioned, set extra accurately oscillating element cost is higher and need extra pin to communicate with it in the existing USB device.The present invention proposes a kind of frequency adjusting device and frequency adjusting method that does not need the adjustable oscillator of plug-in accurate oscillating element in addition, can also immediately adjust the oscillation frequency of adjustable oscillator according to the packet of any type in the usb data stream that is received automatically.
Though the present invention is disclosed by the foregoing description, yet the foregoing description is not that any the technical staff in the technical field of the invention without departing from the spirit and scope of the present invention, should make various variations and modification in order to qualification the present invention.Therefore protection scope of the present invention should be as the criterion with the scope that appended claims was defined.
Claims (23)
1. the frequency adjusting method of an adjustable oscillator, this method comprises the following steps:
Receive usb data stream and clock signal;
Estimate the accumulative total bit number that described usb data flows according to this clock signal, and the over-sampling number of described clock signal is counted;
When described accumulative total bit number during more than or equal to preset value, the doubly described totally bit number of more described over-sampling number and M;
When described over-sampling number adds up bit number greater than M is doubly described, reduce the frequency of described clock signal; And
When described over-sampling number adds up bit number less than M is doubly described, promote the frequency of described clock signal.
2. frequency adjusting method according to claim 1, wherein, described preset value is at least 23.
3. frequency adjusting method according to claim 1, wherein, in the step of the accumulative total bit number of the described usb data of estimation stream, the bit between first bit of estimating synchronization bit in the packet of described usb data stream and the previous bit of the end bit of dividing into groups.
4. frequency adjusting method according to claim 1, wherein, the step of estimating the accumulative total bit number of described usb data stream according to described clock signal comprises the following steps:
According to pairing over-sampling number between the adjacent transform strike slip boundary in the described usb data stream, estimate the bit number between the adjacent transform strike slip boundary; And
Bit number between the accumulative total continuous adjacent transform strike slip boundary is to obtain described accumulative total bit number.
5. frequency adjusting method according to claim 1, wherein, M is a dividend for the expected frequency with described clock signal, and the data transfer rate that flows with described usb data is the merchant of divisor.
6. frequency adjusting method according to claim 1 wherein, in the step of the accumulative total bit number of estimating described usb data stream according to described clock signal, estimate the data type that described accumulative total bit number and described usb data stream comprises and is had nothing to do.
7. frequency adjusting method according to claim 1, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
8. the frequency adjusting method of an adjustable oscillator, this method are used for adjusting the oversampled signals that adjustable oscillator sends according to usb data stream, and this frequency adjusting method comprises the following steps:
Over-sampling number to described oversampled signals is counted, and estimates the accumulative total bit number of described usb data stream according to described oversampled signals;
When this adds up bit number more than or equal to preset value, calculate the difference of the doubly described accumulative total of described over-sampling number and M bit number; And
Determine the frequency of described oversampled signals to adjust the lattice number according to this difference.
9. frequency adjusting method according to claim 8, wherein, described preset value is at least 23.
10. frequency adjusting method according to claim 8, wherein, estimate in the step of accumulative total bit number of described usb data stream the bit between first bit of estimating synchronization bit in the packet of described usb data stream and the previous bit of the end bit of dividing into groups according to described oversampled signals.
11. frequency adjusting method according to claim 8, wherein, the step of estimating the accumulative total bit number of described usb data stream according to described oversampled signals comprises the following steps:
According to pairing over-sampling number between the adjacent transform strike slip boundary in the described usb data stream, estimate the bit number between the adjacent transform strike slip boundary; And
Bit number between the accumulative total continuous adjacent transform strike slip boundary is to obtain described accumulative total bit number.
12. frequency adjusting method according to claim 8, this method also comprises the following steps:
Adjust the lattice number greater than 1 the time when described frequency, adjust the oversampled signals of described adjustable oscillator; And
Adjust the lattice number less than 1 the time when described frequency, keep the oversampled signals of described adjustable oscillator.
13. frequency adjusting method according to claim 8, wherein, a frequency is adjusted the frequency adjustment resolution that the lattice number is described adjustable oscillator.
14. frequency adjusting method according to claim 13, wherein, described frequency is adjusted the lattice number and is defined as (the doubly described accumulative total of described difference/M bit number)/(described frequency is adjusted the M haplotype data rate of resolution/described usb data stream).
15. frequency adjusting method according to claim 8, wherein, M is a dividend for the expectation over-sampling frequency with described adjustable oscillator, and the data transfer rate that flows with described usb data is the merchant of divisor.
16. frequency adjusting method according to claim 8 wherein, in the step of the accumulative total bit number of estimating described usb data stream according to described oversampled signals, estimate the data type that described accumulative total bit number and described usb data stream comprises and is had nothing to do.
17. frequency adjusting method according to claim 8, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
18. the frequency adjusting device of an adjustable oscillator, this device are used for adjusting according to usb data stream the oscillation frequency of adjustable oscillator, this frequency adjusting device comprises:
The counting processing unit is counted the vibration number of described adjustable oscillator, estimates the accumulative total bit number that described usb data flows according to this vibration number, and relatively M doubly should add up bit number and described vibration number, adjusted the lattice number with output frequency; And
Controller is coupled between described counting processing unit and the described adjustable oscillator, adjusts the oscillation frequency that the lattice number is adjusted described adjustable oscillator according to described frequency.
19. frequency adjusting device according to claim 18, wherein, the arbitrary data grouping that described usb data stream is exported for usb host.
20. frequency adjusting device according to claim 18, wherein, a frequency is adjusted the frequency adjustment resolution that the lattice number is described adjustable oscillator.
21. frequency adjusting device according to claim 20, wherein, described frequency is adjusted the lattice number and is defined as (the doubly described accumulative total of the difference/M bit number of M doubly described accumulative total bit number and described vibration number)/(described frequency is adjusted the M haplotype data rate of resolution/described data stream).
22. according to claim 18 or 21 described frequency adjusting devices, wherein, M is a dividend for the expectation oscillation frequency with described adjustable oscillator, and the data transfer rate that flows with described usb data is the merchant of divisor.
23. frequency adjusting device according to claim 18, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
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| CN 200910222682 CN102081426B (en) | 2009-11-30 | 2009-11-30 | Frequency adjustment device and frequency adjustment method for adjustable oscillator |
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| CN102081426B CN102081426B (en) | 2013-06-12 |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103677079A (en) * | 2012-09-14 | 2014-03-26 | 原相科技股份有限公司 | Frequency calibration device and method for programmable oscillator |
| CN104320203A (en) * | 2014-03-24 | 2015-01-28 | 贾宏勇 | Wireless frequency calibration device and method |
| CN105823473A (en) * | 2015-01-22 | 2016-08-03 | 精工爱普生株式会社 | Circuit device, electronic apparatus, moving object and method of manufacturing of physical quantity detection device |
| CN110800247A (en) * | 2017-07-03 | 2020-02-14 | 索尼半导体解决方案公司 | Transmitter and transmitting method, and receiver and receiving method |
| CN111290984A (en) * | 2018-12-07 | 2020-06-16 | 新唐科技股份有限公司 | Universal serial bus device and operation method thereof |
| CN111800248A (en) * | 2020-05-28 | 2020-10-20 | 韦臣龙 | Communication method and device based on virtual carrier data mode |
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| US6407641B1 (en) * | 2000-02-23 | 2002-06-18 | Cypress Semiconductor Corp. | Auto-locking oscillator for data communications |
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| US7093151B1 (en) * | 2000-09-22 | 2006-08-15 | Cypress Semiconductor Corp. | Circuit and method for providing a precise clock for data communications |
| CN1508965A (en) * | 2002-12-18 | 2004-06-30 | 安国国际科技股份有限公司 | Self-regulating oscillator for USB connecting interface |
| CN100341005C (en) * | 2003-12-11 | 2007-10-03 | 安国国际科技股份有限公司 | Method for automatic adjusting oscillator |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| US6407641B1 (en) * | 2000-02-23 | 2002-06-18 | Cypress Semiconductor Corp. | Auto-locking oscillator for data communications |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103677079A (en) * | 2012-09-14 | 2014-03-26 | 原相科技股份有限公司 | Frequency calibration device and method for programmable oscillator |
| CN103677079B (en) * | 2012-09-14 | 2017-05-24 | 原相科技股份有限公司 | Frequency calibration device and method for programmable oscillator |
| CN104320203A (en) * | 2014-03-24 | 2015-01-28 | 贾宏勇 | Wireless frequency calibration device and method |
| CN104320203B (en) * | 2014-03-24 | 2017-04-12 | 上海巨微集成电路有限公司 | Wireless frequency calibration device and method |
| CN105823473A (en) * | 2015-01-22 | 2016-08-03 | 精工爱普生株式会社 | Circuit device, electronic apparatus, moving object and method of manufacturing of physical quantity detection device |
| CN110800247A (en) * | 2017-07-03 | 2020-02-14 | 索尼半导体解决方案公司 | Transmitter and transmitting method, and receiver and receiving method |
| CN111290984A (en) * | 2018-12-07 | 2020-06-16 | 新唐科技股份有限公司 | Universal serial bus device and operation method thereof |
| CN111800248A (en) * | 2020-05-28 | 2020-10-20 | 韦臣龙 | Communication method and device based on virtual carrier data mode |
| CN111800248B (en) * | 2020-05-28 | 2023-03-14 | 韦臣龙 | Communication method and device based on virtual carrier data mode |
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| CN102081426B (en) | 2013-06-12 |
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