CN102081426B - Frequency adjustment device and frequency adjustment method for adjustable oscillator - Google Patents
Frequency adjustment device and frequency adjustment method for adjustable oscillator Download PDFInfo
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- CN102081426B CN102081426B CN 200910222682 CN200910222682A CN102081426B CN 102081426 B CN102081426 B CN 102081426B CN 200910222682 CN200910222682 CN 200910222682 CN 200910222682 A CN200910222682 A CN 200910222682A CN 102081426 B CN102081426 B CN 102081426B
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Abstract
The invention relates to a frequency adjustment method for an adjustable oscillator. The method comprises the following steps of: counting the oversampling number of an oversampling signal, and estimating the accumulated bit number of universal serial bus (USB) data stream according to the oversampling signal; when the accumulated bit number is more than or equal to a preset value, calculating the difference of the oversampling number and M times the accumulated bit number; and determining the frequency adjustment lattice number of the oversampling signal according to the difference. In addition, the invention provides a frequency adjustment device for the adjustable oscillator. By the frequency adjustment device and the frequency adjustment method, an accurate oscillating element is not required to be hung, and the oscillating frequency of the adjustable oscillator can be automatically and instantaneously adjusted according to any type of data packet in the received USB data stream.
Description
Technical field
The present invention relates to a kind of data transmission structure and method, and relate in particular to a kind of frequency adjusting device and frequency adjusting method of automatically adjusting the oscillation frequency of adjustable vibration device according to data stream.
Background technology
Use the oscillatory circuit of outside sequential can be in order to clock signal to be provided, and this oscillatory circuit uses plug-in accurate sequential element usually, for example crystal oscillator (crystal resonator) or ceramic resonator (ceramic resonator), provide reference frequency to this oscillatory circuit.Yet, use plug-in accurate sequential element not only can increase system cost, and one or two pins (pin) also must be set in addition with as the interface of communicating by letter with this accurate sequential element on the control chip of oscillatory circuit.
Control chip for example also can utilize phase-locked loop (PLL) or delay phase-locked loop road (DLL) internal frequency to be adjusted to consistent with the data transfer rate (data rate) of the data stream that receives except the reference frequency that can use plug-in accurate sequential element and provide; Yet the method need to spend the long adjustment time usually, thereby and be not suitable for some application, for example on the USB device.
In view of this, be necessary to propose a kind ofly need not use the plug-in accurate sequential element still can be fast and automatically adjust frequency adjusting device and the frequency adjusting method of the oscillation frequency of adjustable vibration device, to solve existing problem in prior art.
Summary of the invention
The object of the invention is to propose a kind of frequency adjusting device and frequency adjusting method that need not use the adjustable vibration device of plug-in oscillator, it can according to the packet of any type in the usb data stream that receives, adjust the oscillation frequency of adjustable vibration device automatically.
The object of the invention is to propose a kind of frequency adjusting device and frequency adjusting method of adjustable vibration device, it can immediately adjust the oscillation frequency of adjustable vibration device during data transmission, cause frequency drift to avoid the adjustable vibration device because of environmental change.
The present invention proposes a kind of frequency adjusting method of adjustable vibration device, and the method comprises the following steps: to receive usb data stream and clock signal; According to the accumulative total bit number of this clock signal estimation usb data stream, and the over-sampling number of clock signal is counted; When this adds up bit number more than or equal to preset value, compare doubly described accumulative total bit number of over-sampling number and M; Serve as hits and doubly during described accumulative total bit number, reduced the frequency of clock signal greater than M; And served as hits and doubly during described accumulative total bit number, promoted the frequency of clock signal less than M.
The another frequency adjusting method that proposes a kind of adjustable vibration device of the present invention is in order to adjust according to usb data stream the oversampled signals that the adjustable vibration device sends.This frequency adjusting method comprises the following steps: the over-sampling number of oversampled signals is counted, and estimates the accumulative total bit number of usb data stream according to oversampled signals; When this adds up bit number more than or equal to preset value, calculate the doubly difference of described accumulative total bit number of over-sampling number and M; And the frequency adjustment lattice number that determines oversampled signals according to this difference.
The another frequency adjusting device that proposes a kind of adjustable vibration device of the present invention is in order to adjust the oscillation frequency of adjustable vibration device according to usb data stream.This frequency adjusting device comprises counting processing unit and controller.Described counting processing unit is counted the vibration number of adjustable vibration device, and according to the accumulative total bit number of this vibration number estimation usb data stream, and relatively M doubly is somebody's turn to do accumulative total bit number and vibration number, adjusts the lattice number with output frequency.Described controller is coupled between counting processing unit and adjustable vibration device, adjusts according to described frequency the oscillation frequency that the lattice number is adjusted described adjustable vibration device.
In the frequency adjusting device and frequency adjusting method of adjustable vibration device of the present invention, utilize the packet (data packet) of any type of USB (universal serial bus) (USB), for example, but be not limited to, set in grouping (SETUP packet), packet (DATA packet) and output grouping (OUT packet), finish between idle (Idle) bit and grouping the foundation that the bit between (EOP) bit is adjusted as frequency, so need not use plug-in accurate sequential element in the present invention.Frequency adjusting device of the present invention and frequency adjusting method are applicable to use the device of USB (universal serial bus), for example the USB mouse.
Description of drawings
Fig. 1 has shown the calcspar of the self-adjustable oscillatory circuit of an embodiment of the present invention;
Fig. 2 a has shown the partial data stream that usb host is exported;
Fig. 2 b has shown the graph of a relation of the data stream of the oversampled signals of USB device and Fig. 2 a;
Fig. 3 has shown maximum jitter budget required in the low speed transmissions;
Fig. 4 has shown the corresponding bit number of over-sampling number between the adjacent transform strike slip boundary of usb data stream in the present invention;
Fig. 5 has shown the schematic diagram of frequency adjusting method of the adjustable vibration device of the embodiment of the present invention;
Fig. 6 has shown the process flow diagram of frequency adjusting method of the adjustable vibration device of an embodiment of the present invention;
Fig. 7 has shown the process flow diagram of frequency adjusting method of the adjustable vibration device of the another kind of embodiment of the present invention; And
Fig. 8 has shown through the maximum frequency error after frequency adjusting method adjustment once of the present invention.
The main element symbol description
1 self-adjustable oscillatory circuit 101 input ends
102 output terminal 103 feedback input ends
104 control output end 11 frequency adjusting devices
111 counting processing unit 112 controllers
12 adjustable vibration device S
1Control signal
S
2Frequency is adjusted lattice and is counted Data USB data stream
CLK clock signal between the CI count block
Embodiment
For allow above and other purpose of the present invention, feature and advantage can be more obvious, hereinafter will coordinate appended diagram, be described in detail below.In addition, in explanation of the present invention, identical member is with identical symbolic representation, in this close first chat bright.
According to universal serial bus specification (Universal Serial Bus Specification, version 1.1) contained, the data transfer rate error of low speed USB device must can correctly operate in ± 1.5%, the data transfer rate error of including simultaneously usb host in is that the error of the built-in oscillator of ± 0.25%, one low speed USB device must be maintained at ± can guarantee in 1.25% USB interface and correctly carries out data transmission.Therefore, if the over-sampling frequency of hypothesis USB device is 24MHz (16 times of over sampling ratio), the oscillation frequency of the built-in oscillator of this USB device must be in the scope of 24MHz ± 300KHz.It must be understood that, the over-sampling frequency of USB device is not defined as 24MHz.
Please refer to shown in Figure 1ly, it has shown the self-adjustable oscillatory circuit 1 of an embodiment of the present invention, and it has input end 101 and output terminal 102.This self-adjustable oscillatory circuit 1 can be built in the USB device, and USB mouse (mouse) for example with as its local oscillator, and produces the adjustable clock signal clk of frequency according to usb data stream Data.This clock signal clk for example recovers the oversampled signals (oversampling signal) of (datarecovery) for being used for data.
Described input end 101 is in order to receive data stream (data stream) Data from usb host, and described output terminal 102 is in order to clock signal CLK.Error between the data transfer rate of the frequency of this clock signal clk and data stream Data (data rate) for example can be adjusted to data stream Data M haplotype data rate 0.805%～1.027% between, wherein M is for representing the positive integer of over sampling ratio (oversampling ratio).Data stream Data for example for any type of packet in usb data stream, for example sets the grouping of grouping (SETUP packet), output grouping (OUT packet), packet (DATA packet) or other types.In a kind of embodiment, described data stream Data for example can be low speed (lowspeed) data stream, and its data transfer rate is 1.5MHz.
Described self-adjustable oscillatory circuit 1 comprises frequency adjusting device 11 and the adjustable vibration device 12 that mutually couples.This adjustable vibration device 12 for example can be RC oscillator or other suitable adjustable vibration devices.Described frequency adjusting device 11 flows Data from the usb data that input end 101 receives from usb host.Described frequency adjusting device 11 comprises feedback input end 103 and control output end 104.Frequency adjusting device 11 self-feedback input ends 103 receive feedback from the clock signal clk of adjustable vibration device 12, and certainly control output terminal 104 output control signal S
1To adjustable vibration device 12, control signal S wherein
1For example can be the digital controlled signal that comprises a plurality of bits.Adjustable vibration device 12 is according to control signal S
1Clock signal CLK is with the reference frequency as the USB device.
Please be simultaneously with reference to shown in Fig. 2 a and Fig. 2 b, Fig. 2 a has shown that usb host (USB host) is sent to the schematic diagram of the packet of USB device (USB device), comprise one herein and set grouping (SETUP packet) and an output grouping (OUTPUT packet), but in fact also may comprise the packet of other any types.Fig. 2 b has shown the relation of part enlarged drawing and 24MHz over-sampling frequency and the 1.5MHz data stream Data of Fig. 2 a, that is in this embodiment, the built-in oscillator of USB device will be obtained 16 oversampled points between each bit period of a data grouping under situation accurately.
Please be simultaneously with reference to shown in Fig. 1, Fig. 2 a and Fig. 2 b, counting processing unit 111 CI between a count block counts the over-sampling number between the clock signal clk of the bit number between first bit of synchronous (SYNC) bit and the previous bit of grouping end (EOP) bit and feedback in the packet of any type of data stream Data simultaneously, and relation more between the two, adjust lattice with the frequency that determines adjustable vibration device 12 and count S
2112 of controllers are adjusted lattice according to frequency and are counted S
2Carry out the oscillation frequency adjustment of adjustable vibration device 12; Wherein, if between a count block, CI comprises N bit at least, when first packet in CI between this count block (for example set grouping) from synchronization bit to the previous bit of the end bit of dividing into groups during (bit number of SYNC+PID+ADDR+ENDP+CRC5 as Fig. 2 a) not enough N bit, stop counting when receiving the grouping end bit, and when first bit (as the output grouping in Fig. 2 a) of the synchronization bit that receives once again next packet, begin once again counting, until number stops to greater than N bit the time.
Have shake (jitter) due to data stream Data, so the bit number that between each count block, CI comprises must be able to be allowed the jitter budget (jitter budget) under the poorest condition (worst-case) when transmitting.Please refer to shown in Figure 3, it has shown data stream through the hub (HUB) of 5 serial connections and has transmitted continuous 1 situation, and with regard to the USB normalized definition, continuous six 1 can be inserted one 0, be so-called bit padding (Bit stuffing), be the poorest condition this moment.As we know from the figure, have the maximum time shake when changing (paired transition) in pairs, it is 184ns.In low speed transmissions, if will shake time and data transfer rate permission (184/ (666.66 * 1.25%)=22.08 bit) divided by each bit in data stream Data maximum time, can obtain when low speed transmissions that between a count block, CI is minimum must comprise 23 bits, can avoid occuring the situation of miscount.The detailed content of Fig. 3 is recorded in universal serial bus specification the 1.1st edition.
In the present invention, in CI, the mode of the bit number of estimation data stream Data is to be undertaken by the bit number of estimating the bit number between adjacent transform strike slip boundary (transition edge) and add up between the continuous adjacent transform strike slip boundary between a count block.Adopt the coded system of non-return-to-zero reversal phase coding (Non return to zero, NRZI) due to packet in USB (universal serial bus), it may include at most 6 continuous 1.When continuous bit 1 appears in data stream Data, transform strike slip boundary can not occur during continuous 1, so the present invention need to carry out the bit number estimation for the data of successive bits 1.
Please be simultaneously with reference to Fig. 2 a, Fig. 2 b and shown in Figure 4, Fig. 4 has shown the corresponding bit number of over-sampling number between the adjacent transform strike slip boundary of usb data stream in the present invention.When the frequency error that dispatches from the factory of adjustable vibration device 12 is adjusted to lower than 3% the time, counting processing unit 111 can be according to the bit number between the adjacent transform strike slip boundary of setting estimation of Fig. 4 according to the bit number in clock signal clk estimation data stream Data the time.As shown in Figure 4, during lower than 24,111 judgements of counting processing unit only comprise 1 bit when the over-sampling number between two adjacent continuous transform strike slip boundaries; When the over-sampling number between two continuous transform strike slip boundaries was between 24 and 40,111 judgements of counting processing unit comprised 2 bits; ...; During greater than 104,111 judgements of counting processing unit comprise 7 bits when the over-sampling number between two continuous transform strike slip boundaries, and this moment, data stream was 6 continuous 1 and 10.By this, 111 of processing units of counting can according in data stream Data between adjacent transform strike slip boundary corresponding over-sampling number estimate bit number between two adjacent transform strike slip boundaries, and the bit number of continuous adjacent transform strike slip boundary is added up, to obtain the accumulative total bit number.
Please be simultaneously with reference to Fig. 1, Fig. 2 a, Fig. 2 b and shown in Figure 5, Fig. 5 has shown the schematic diagram of frequency adjusting method of the adjustable vibration device of the embodiment of the present invention.Counting processing unit 111 is adjusted the oscillation frequency of the clock signal clk that adjustable vibration device 12 produces according to the usb data that receives stream Data and clock signal clk.
Step S
210: counting processing unit 111 receives usb data stream and clock signal, over-sampling number to this clock signal clk is counted, and according to the accumulative total bit number in the over-sampling number of clock signal clk estimation data stream Data, wherein estimate the data type (pattern) that this accumulative total bit number and data stream Data comprise and have nothing to do.Counting processing unit 111 estimate the bit number between adjacent transform strike slip boundary according to corresponding over-sampling number between two adjacent transform strike slip boundaries in Fig. 4, and the bit number between accumulative total continuous adjacent transform strike slip boundary, to obtain totally bit number.
Step S
220: whether counting processing unit 111 judgement accumulative total bit numbers greater than preset value, wherein according to Fig. 3 as can be known this preset value be at least 23.Greater than preset value, enter step S when the accumulative total bit number
230
Step S
230: counting processing unit 111 judges whether the over-sampling number doubly adds up bit number greater than M, wherein M is for take the system frequency of the expectation oscillation frequency of adjustable vibration device 12 or USB device as dividend, and the business take the data transfer rate of data stream Data as divisor, that is over sampling ratio (oversamplingratio).For example in Fig. 2 b, M is 16.When having served as hits and doubly having added up bit number greater than M, execution in step S
240～S
243, to reduce the oscillation frequency of clock signal clk; When having served as hits and doubly having added up bit number less than M, execution in step S
250～S
253, to promote the oscillation frequency of clock signal clk.
Step S
240: when having served as hits and doubly adding up bit number greater than M, the over-sampling number is deducted M doubly add up bit number in the hope of the first difference.
Step S
241: counting processing unit 111 is tried to achieve and is reduced the lattice number, and is sent to controller 112, wherein reduces lattice number=(the first difference/M doubly adds up bit number)/(frequency is adjusted the M haplotype data rate of resolution/data stream).One is reduced the lattice numerical example as being the frequency adjustment resolution (resolution) of adjustable vibration device 12.For example in low speed transmissions, M can be 16, and the M haplotype data rate of data stream can be 24MHz, but the present invention is not limited to this.
Step S
242: counting processing unit 111 judges that whether reduction lattice number is less than 1; If, execution in step S
260If not, execution in step S
243
Step S
243: judge when counting processing unit 111 and reduce the lattice numbers greater than 1 the time, transmit these reduction lattice and count S
2To controller 112.112 of this controllers send control signal S according to this
1Reduce the oscillation frequency of adjustable vibration device 12.Simultaneously, 111 of processing units of counting are again by step S
210Beginning adjustment next time.In a kind of embodiment, each reduces lattice number can be between 110KHz～140KHz, but is not limited to this.In a kind of embodiment, when the reduction lattice number of obtaining is not positive integer, can uses rounding-off method or directly fraction part be removed so that this reduction lattice number becomes positive integer.
Step S
260: judge when counting processing unit 111 and reduce the lattice numbers less than 1 the time, the oscillation frequency that represents adjustable vibration device 12 is stable and do not adjust.Then, counting processing unit 111 is begun again the over-sampling number of clock signal clk to be counted by the next bit of CI between the count block of completing counting, the accumulative total bit number of estimation usb data stream, and from step S
210Carry out correction next time; Be understandable that, if between the count block last bit of CI be just CRC5 (during with reference to a) last bit of Fig. 2, between next count block from first bit of the SYNC of next packet.
Step S
250: when having served as hits and doubly adding up bit number less than M, M is doubly added up bit number deduct the over-sampling number in the hope of the second difference.
Step S
251: counting processing unit 111 is tried to achieve the Upgrade Lattice number, and is sent to controller 112, wherein the Upgrade Lattice number=(the second difference/M doubly adds up bit number)/(frequency is adjusted the M haplotype data rate of resolution/data stream).A Upgrade Lattice numerical example is as being the frequency adjustment resolution of adjustable vibration device 12.
Step S
252: counting processing unit 111 judges that whether the Upgrade Lattice number is less than 1; If, execution in step S
260If not, execution in step S
253
Step S
253: when counting processing unit 111 judges that the Upgrade Lattice numbers greater than 1 the time, transmit the Upgrade Lattice and count S
2To controller 112.112 of controllers send control signal S according to this
1, the oscillation frequency of lifting adjustable vibration device 12.Simultaneously, 111 of processing units of counting are again by step S
210Beginning adjustment next time.In a kind of embodiment, each the Upgrade Lattice number can be between 110KHz～140KHz, but is not limited to this.In a kind of embodiment, when the Upgrade Lattice number of obtaining is not positive integer, can uses rounding-off method or directly fraction part be removed so that this Upgrade Lattice number becomes positive integer.
Therefore, the frequency adjusting method of the adjustable vibration device of an embodiment of the present invention comprises the following steps: to receive usb data stream and clock signal (step S as shown in Figure 6
310); According to the accumulative total bit number of this clock signal estimation usb data stream, and the over-sampling number of clock signal is counted (step S
320); When adding up bit number greater than preset value, relatively over-sampling number and M doubly add up bit number (step S
330); When having served as hits and doubly adding up bit number greater than M, reduce frequency (the step S of clock signal
340); And when having served as hits and doubly adding up bit number less than M, promote frequency (the step S of clock signal
350).The detailed embodiment of the present embodiment has been illustrated in Fig. 5 and related description thereof, therefore repeat no more in this.
The frequency adjusting method of the adjustable vibration device of the another kind of embodiment of the present invention as shown in Figure 7, this frequency adjusting method adjusts in order to according to usb data stream the oversampled signals that the adjustable vibration device sends.This frequency adjusting method comprises the following steps: the over-sampling number of oversampled signals is counted, and estimates accumulative total bit number (the step S of usb data stream according to oversampled signals
410); When this adds up bit number greater than preset value, calculate over-sampling number and M and doubly add up difference (the step S of bit number
420); And frequency adjustment lattice number (the step S that determines oversampled signals according to this difference
430).
Please refer to shown in Figure 8ly, it has shown through after frequency adjusting device of the present invention and method adjustment once, the maximum error of adjustable vibration device 12; Wherein, when initial error was between 1%～3%, the error after adjustment once of the present invention can be between 0.805%～1.027%.In Fig. 8, between the count block, CI is grouped into example (totally 64 bits) with two inputs that comprise 32 bits, the system frequency of low speed USB device (being the oscillation frequency of adjustable oscillator 12) is assumed to be 24MHz (the over-sampling cycle was 41.667 nanoseconds), that is 16 times of over sampling ratios.In the frequency adjusting device and method of adjustable vibration device of the present invention, the initial error of adjustable vibration device 12 (initial error) preferably is adjusted into lower than 3%, so that counting processing unit 111 can be estimated correct bit number between adjacent transform strike slip boundary according to Fig. 4.In addition, in the present embodiment, the frequency of adjustable vibration device 12 is adjusted the resolution hypothesis between 110KHz～140KHz, but the present invention is not limited to this.
The initial error of adjustable vibration device 12 is 1%～3%, and it is shown in the first row of Fig. 8.Now take the account form of initial error 1% as the first row of example key diagram 8, and the account form of other each row is all identical, therefore repeat no more.In secondary series, the desirable bit time of 64 bits is 64 * (1/1.5MHz)=42667 nanoseconds (ns).
In the 3rd row, meta-maximum jitter time, i.e. 42667-184=42483 nanosecond when when considering shake, the shortest time of 64 bits is desirable bit; Wherein, the maximum jitter time please refer to Fig. 3.
In the 4th row, when considering shake, the maximum duration of 64 bits is desirable bit time+maximum jitter time, i.e. 42667+184=42851 nanosecond.
The 5th classifies between the count block minimum over-sampling number in CI as, equals (bit shortest time * (1-initial error)/over-sampling cycle)-sampling error; In the present embodiment, each packet of hypothesis has the sampling error of 1 bit, and therefore the sampling error of 2 input groupings is 2.Minimum over-sampling number=42483 * (1-1%)/41.667)-2=1007.
The 6th classifies between the count block maximum over-sampling number in CI as, equals (bit maximum duration * (1+ initial error)/over-sampling cycle)+sampling error, namely equals 42851 * (1+1%)/41.667ns)+2=1041.
The 7th row and the 8th row are respectively minimum value and the maximal value of clock minimum zone, wherein minimum value=(minimum over-sampling number-1) * 1000/ bit maximum duration, i.e. (1007-1) * 1000/42851=23.477MHz; Maximal value=(minimum over-sampling number-1) * 1000/ bit shortest time, i.e. (1007-1) * 1000/42483=23.680MHz.
The 9th row and the tenth row are respectively minimum value and the maximal value of clock maximum magnitude, wherein minimum value=(maximum over-sampling number-1) * 1000/ bit maximum duration, i.e. (1041-1) * 1000/42851=24.270MHz; Maximal value=(maximum over-sampling number-1) * 1000/ bit shortest time, i.e. (1041-1) * 1000/42483=24.480MHz.
The 11 classifies the Upgrade Lattice number with respect to different initial errors as.
Minimum frequency and the maximum frequency of oscillation frequency after the 12 row and 13 row are respectively and promote.The minimum value of minimum frequency=clock minimum zone+the Upgrade Lattice number * minimum resolution is 23.477MHz+3 * 110KHz=23.807MHz; The maximal value of maximum frequency=clock minimum zone+the Upgrade Lattice number * maximum resolution is 23.680MHz+3 * 140KHz=24.100MHz.
The 14 classifies the reduction lattice number with respect to different initial errors as.
Minimum frequency and the maximum frequency of oscillation frequency after the 15 row and 16 row are respectively and reduce.The minimum value of minimum frequency=clock maximum magnitude-reduction lattice number * maximum resolution is 24.270MHz-3 * 140KHz=23.850MHz; The maximal value of maximum frequency=clock maximum magnitude-reduction lattice number * minimum resolution is 24.480MHz-3 * 110KHz=24.150MHz.
The 17 classifies the maximum error of adjusting rear oscillation frequency as, the minimum frequency of frequency after maximum error betides and promotes herein, so maximum error is 100% * (24-23.807)/24=0.805%.
Be understandable that, although describe with low speed transmissions in the present invention, it is only exemplary; Frequency adjusting device of the present invention and method are not limited to low speed USB device.
As previously mentioned, in existing USB device, set extra accurately oscillating element cost is higher and need extra pin to communicate with it.Another a kind of frequency adjusting device and frequency adjusting method that does not need the adjustable vibration device of plug-in accurate oscillating element, the automatic oscillation frequency that also immediately adjust the adjustable vibration device of packet of any type in can flowing according to the usb data that receives of proposing of the present invention.
Although the present invention is disclosed by above-described embodiment, yet above-described embodiment is not to limit the present invention, any the technical staff in the technical field of the invention without departing from the spirit and scope of the present invention, should make various variations and modification.Therefore protection scope of the present invention should be as the criterion with the scope that appended claims was defined.
Claims (21)
1. the frequency adjusting method of an adjustable vibration device, the method comprises the following steps:
Receive the clock signal of usb data stream and the output of adjustable vibration device;
According to the accumulative total bit number of the bit between the previous bit of first bit of synchronization bit in the packet of the described usb data stream of this clock signal estimation and the end bit of dividing into groups, and the over-sampling number of described clock signal is counted;
When described accumulative total bit number during more than or equal to preset value, more described over-sampling number and M be described accumulative total bit number doubly, wherein, M is the positive integer of over sampling ratio, and described preset value is the bit number that comprises at least during the jitter budget under allowing the poorest condition between a count block;
When described over-sampling number doubly during described accumulative total bit number, reduces the frequency of described clock signal greater than M; And
When described over-sampling number doubly during described accumulative total bit number, promotes the frequency of described clock signal less than M.
2. frequency adjusting method according to claim 1, wherein, the time that is dithered as 184ns, each bit when maximum time is 666.66ns and data transfer rate permission when being 1.25%, described preset value is at least 23.
3. frequency adjusting method according to claim 1 wherein, comprises the following steps: according to the step of the accumulative total bit number of the described usb data stream of described clock signal estimation
In flowing according to described usb data, corresponding over-sampling number between adjacent transform strike slip boundary, estimate the bit number between adjacent transform strike slip boundary; And
Bit number between accumulative total continuous adjacent transform strike slip boundary is to obtain described accumulative total bit number.
4. frequency adjusting method according to claim 1, wherein, M is for take the expected frequency of described clock signal as dividend, and the business take the data transfer rate of described usb data stream as divisor.
5. frequency adjusting method according to claim 1 wherein, in the step according to the accumulative total bit number of the described usb data stream of described clock signal estimation, estimate the data type that described accumulative total bit number and described usb data stream comprises and is had nothing to do.
6. frequency adjusting method according to claim 1, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
7. the frequency adjusting method of an adjustable vibration device, the method are used for adjusting according to usb data stream the oversampled signals that the adjustable vibration device sends, and this frequency adjusting method comprises the following steps:
Over-sampling number to described oversampled signals is counted, and the accumulative total bit number of the bit between the previous bit of first bit and the end bit of dividing into groups of synchronization bit in the packet of usb data stream according to the estimation of described oversampled signals;
When this adds up bit number more than or equal to preset value, calculate the doubly difference of described accumulative total bit number of described over-sampling number and M, wherein, M is the positive integer of over sampling ratio, and described preset value is the bit number that comprises at least during the jitter budget under allowing the poorest condition between a count block; And
The frequency that determines described oversampled signals according to this difference is adjusted the lattice number.
8. frequency adjusting method according to claim 7, wherein, the time that is dithered as 184ns, each bit when maximum time is 666.66ns and data transfer rate permission when being 1.25%, described preset value is at least 23.
9. frequency adjusting method according to claim 7 wherein, comprises the following steps: according to the step of the accumulative total bit number of the described usb data stream of described oversampled signals estimation
In flowing according to described usb data, corresponding over-sampling number between adjacent transform strike slip boundary, estimate the bit number between adjacent transform strike slip boundary; And
Bit number between accumulative total continuous adjacent transform strike slip boundary is to obtain described accumulative total bit number.
10. frequency adjusting method according to claim 7, the method also comprises the following steps:
Adjust the lattice number greater than 1 the time when described frequency, adjust the oversampled signals of described adjustable vibration device; And
Adjust the lattice number less than 1 the time when described frequency, keep the oversampled signals of described adjustable vibration device.
11. frequency adjusting method according to claim 7, wherein, a frequency is adjusted the frequency adjustment resolution that the lattice number is described adjustable vibration device.
12. frequency adjusting method according to claim 7, wherein, described frequency adjustment lattice are several calculates according to following formula: (described difference/M is described accumulative total bit number doubly)/(frequency of described adjustable vibration device is adjusted the M haplotype data rate of resolution/described usb data stream).
13. frequency adjusting method according to claim 7, wherein, M is for take the expectation over-sampling frequency of described adjustable vibration device as dividend, and the business take the data transfer rate of described usb data stream as divisor.
14. frequency adjusting method according to claim 7 wherein, in the step of the accumulative total bit number of usb data stream according to the estimation of described oversampled signals, estimate the data type that described accumulative total bit number and described usb data stream comprises and is had nothing to do.
15. frequency adjusting method according to claim 7, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
16. the frequency adjusting device of an adjustable vibration device, this device is used for adjusting according to usb data stream the oscillation frequency of adjustable vibration device, and this frequency adjusting device comprises:
The counting processing unit, vibration number to described adjustable vibration device is counted, accumulative total bit number according to the bit between the previous bit of first bit of synchronization bit in the packet of the described usb data stream of this vibration number estimation and the end bit of dividing into groups, and doubly this accumulative total bit number and described vibration number of M relatively during the bit number that comprises at least when allowing jitter budget under the poorest condition between described accumulative total bit number is more than or equal to a count block, adjust the lattice number with output frequency, wherein, M is the positive integer of over sampling ratio; And
Controller is coupled between described counting processing unit and described adjustable vibration device, adjusts according to described frequency the oscillation frequency that the lattice number is adjusted described adjustable vibration device.
17. frequency adjusting device according to claim 16, wherein, the arbitrary data grouping that described usb data stream is exported for usb host.
18. frequency adjusting device according to claim 16, wherein, a frequency is adjusted the frequency adjustment resolution that the lattice number is described adjustable vibration device.
19. frequency adjusting device according to claim 16, wherein, described frequency adjusts that lattice are several to be calculated according to following formula: (M is difference/M described accumulative total bit number doubly of described accumulative total bit number and described vibration number doubly)/(the M haplotype data rate of the frequency adjustment resolution/described data stream of described adjustable vibration device).
20. according to claim 16 or 19 described frequency adjusting devices, wherein, M is for take the expectation oscillation frequency of described adjustable vibration device as dividend, and the business take the data transfer rate of described usb data stream as divisor.
21. frequency adjusting device according to claim 16, wherein, described usb data stream meets non-return-to-zero reversal phase coding specification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910222682 CN102081426B (en) | 2009-11-30 | 2009-11-30 | Frequency adjustment device and frequency adjustment method for adjustable oscillator |
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| US8907730B2 (en) * | 2010-11-17 | 2014-12-09 | Pixart Imaging Inc | Frequency calibration device and method for programmable oscillator |
| CN104320203B (en) * | 2014-03-24 | 2017-04-12 | 上海巨微集成电路有限公司 | Wireless frequency calibration device and method |
| JP6455174B2 (en) * | 2015-01-22 | 2019-01-23 | セイコーエプソン株式会社 | CIRCUIT DEVICE, ELECTRONIC DEVICE, MOBILE BODY AND PHYSICAL QUANTITY DETECTION DEVICE MANUFACTURING METHOD |
| US11108988B2 (en) * | 2017-07-03 | 2021-08-31 | Sony Semiconductor Solutions Corporation | Transmitter and transmission method and receiver and reception method |
| TWI772574B (en) * | 2018-12-07 | 2022-08-01 | 新唐科技股份有限公司 | Universal serial bus device and operation method thereof |
| CN111800248B (en) * | 2020-05-28 | 2023-03-14 | 韦臣龙 | Communication method and device based on virtual carrier data mode |
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| CN1508965A (en) * | 2002-12-18 | 2004-06-30 | 安国国际科技股份有限公司 | Self-regulating oscillator for USB connecting interface |
| CN1627276A (en) * | 2003-12-11 | 2005-06-15 | 安国国际科技股份有限公司 | Method for automatic adjusting oscillator |
| US7093151B1 (en) * | 2000-09-22 | 2006-08-15 | Cypress Semiconductor Corp. | Circuit and method for providing a precise clock for data communications |
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| US6407641B1 (en) * | 2000-02-23 | 2002-06-18 | Cypress Semiconductor Corp. | Auto-locking oscillator for data communications |
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| US7093151B1 (en) * | 2000-09-22 | 2006-08-15 | Cypress Semiconductor Corp. | Circuit and method for providing a precise clock for data communications |
| CN1508965A (en) * | 2002-12-18 | 2004-06-30 | 安国国际科技股份有限公司 | Self-regulating oscillator for USB connecting interface |
| CN1627276A (en) * | 2003-12-11 | 2005-06-15 | 安国国际科技股份有限公司 | Method for automatic adjusting oscillator |
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