CN103092256A - Clock frequency adjusting circuit and clock frequency adjusting method thereof - Google Patents
Clock frequency adjusting circuit and clock frequency adjusting method thereof Download PDFInfo
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- CN103092256A CN103092256A CN 201110343302 CN201110343302A CN103092256A CN 103092256 A CN103092256 A CN 103092256A CN 201110343302 CN201110343302 CN 201110343302 CN 201110343302 A CN201110343302 A CN 201110343302A CN 103092256 A CN103092256 A CN 103092256A
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Abstract
The invention provides a clock frequency adjusting method which includes the steps: calculating the phase difference between an SOF (start of frame) signal or an EOP (end of program) signal in an external signal and a local signal; counting counting values of the phase difference according to the clock frequency of a local oscillator; and adjusting the clock frequency according to the counting values. The invention further provides a clock frequency adjusting circuit.
Description
Technical field
The present invention relates to a kind of clock frequency regulating circuit and clock frequency method of adjustment thereof, particularly clock frequency regulating circuit and the clock frequency method of adjustment thereof of local oscillator in a kind of automatic adjustment USB device.
Background technology
A USB (universal serial bus) (USB) system links institute by usb host (host) and USB device (device) by USB interface (interface) and forms, wherein the data transmission rate between usb host and USB device must satisfy the data transmission standard, for example in (high speed) device at a high speed, data transmission rate must between 480MHz ± 0.05% between; At full speed (full speed) device in, data transmission rate must between 12MHz ± 0.25% between; And in low speed (low speed) device, data transmission rate must between 1.5MHz ± 1.5% between.At present in order to the clock frequency accuracy of controlling local oscillator in the USB device (local oscillator) to meet a kind of mode of above-mentioned standard, quartz (controlled) oscillator (crystal oscillator) is set in addition to increase the accuracy of clock frequency.Yet, use in the chip of quartz (controlled) oscillator, must set up 1-2 pin (PIN) in order to connecting quartz (controlled) oscillator, thereby have the higher problem of cost.
A kind of known oscillators frequency locking circuit, as United States Patent (USP) the 6th, 297, No. 705 disclosed " with the circuit (Circuit for Locking an Oscillator to a Data Stream) of oscillator locking in data stream ", it utilizes the counter comparative figures to control the output frequency of oscillator and the frequency of USB device, and carry out coarse adjustment and the fine setting of numerically-controlled oscillator output frequency according to described comparative result, until with the Frequency Synchronization of USB device.Yet described circuit must utilize whole packet signal to carry out the frequency adjustment, therefore needs long frequency to adjust the time.
The another kind of known method that is applicable to the adjustment oscillator of low speed USB interface connected system, as United States Patent (USP) the 7th, 127, No. 628 patents disclosed " can automatically adjust the method (Method for Automatically Regulating an Oscillator) of oscillator ", described method comprises: (a) provide voltage controlled oscillator to swing signal in order to the USB device is produced controlled damping in USB interface; (b) the described controlled damping of feedback is swung signal to the frequency comparing unit, and it swings Keep Alive Strobe (gating maintenance) signal in signal and USB interface in order to more controlled damping; (c) signal of the frequency comparing unit being exported inputs to the frequency adjustment unit, adjusts voltage with the signal that is fed back according to described frequency comparing unit and swings the frequency of signal to change controlled damping; (d) repeating step (b) and action (c), make controlled damping swing signal and synchronize with Keep Alive Strobe (gating maintenance) signal in USB interface, reaches fast thus the data transmission synchronization between USB interface and USB device.Yet the method only is defined in the connected system of low speed USB interface.
When the USB device was connected to USB interface, the USB device can be received the USB differential wave, and at first described differential wave has a USB reset signal (reset).Each information frame (frame) after described reset signal is in the time, for example 1 millisecond (ms), no matter whether carry out data transmission, the USB device all can continue to receive KeepAlive (maintenance) signal (low speed variator) or SOF (start of frame, start frame) signal (device at full speed); Speeder can be received the SOF signal in every 125 microseconds (μ s).The present invention namely utilizes this persistent signal, also proposes a kind of clock frequency regulating circuit and clock frequency method of adjustment thereof of automatic adjustment local oscillator, effectively to reduce costs, to simplify the system applies circuit and to dwindle the circuit board size.
Summary of the invention
Purpose of the present invention is at a kind of method that automatic adjustment clock frequency is provided and clock frequency regulating circuit, it arranges the adjustable clock generator of frequency in the control chip of USB device, and according to the Keep Alive signal of USB interface or the clock signal frequency of the described clock generator of SOF signal adjustment, with the degree of accuracy of effective increase clock frequency.
Another purpose of the present invention is at a kind of method that automatic adjustment clock frequency is provided and clock frequency regulating circuit, it only needs to arrange the adjustable clock generator of frequency in the control chip of USB device, and need not use crystal oscillator, reduce costs thus, simplify the system applies circuit and dwindle the circuit board size.
Another purpose of the present invention is providing a kind of clock frequency regulating circuit and clock frequency method of adjustment thereof, it arranges the adjustable clock generator of clock frequency in the control chip of USB device, and according to the described clock frequency of the described clock generator of adjusting offset between the local signal of SOF signal or eop signal and USB device in the data stream of usb host output, with the degree of accuracy of the described clock frequency of effective increase.
Another purpose of the present invention is providing a kind of clock frequency regulating circuit and clock frequency method of adjustment thereof that is applicable to simultaneously low speed, full speed and hi-speed USB interface.
For reaching above-mentioned purpose, the invention provides a kind of clock frequency regulating circuit, comprise frequency generating circuit, data sink and correcting unit.Described frequency generating circuit clock signal and local signal.Described data sink receives usb data and flows and export host signal, and wherein said host signal comprises SOF signal or eop signal.Described correcting unit receives described host signal and described local signal, counts the count value of the phase differential of described host signal and described local signal according to described clock signal, and adjusts described clock signal according to described count value.
According to another characteristics of the present invention, the present invention also provides a kind of clock frequency method of adjustment of clock frequency regulating circuit.Described clock frequency regulating circuit comprises frequency generating circuit, correcting unit and data sink.Described clock frequency method of adjustment comprises the following step: receive usb data with described data sink and flow and produce host signal; Produce local signal and clock signal with described frequency generating circuit; Receive described local signal and described host signal calculating phase differential with described correcting unit, and according to the count value of the described phase differential of described clock signal counting; And the clock frequency of adjusting described clock signal according to described count value.
According to another characteristics of the present invention, the present invention also provides a kind of clock frequency method of adjustment of clock frequency regulating circuit.Described clock frequency regulating circuit comprises clock generator, frequency eliminator, phase delay device, phase detectors, control circuit and data sink.Described clock frequency method of adjustment comprises the following step: receive usb data with described data sink and flow and produce host signal; Produce adjustable clock signal with described clock generator; With described frequency eliminator to described adjustable clock signal frequency elimination to produce signal after frequency elimination; With described phase delay device to described frequency elimination after signal carry out preset phase delay to produce local signal; Receive described host signal and described local signal to calculate phase differential with described phase detectors; And receive described phase differential with described control circuit, according to the count value of the described phase differential of described adjustable clock signal counting, and control described clock generator according to described count value.
Clock frequency regulating circuit of the present invention and clock frequency method of adjustment thereof are carried out the adjustment of clock frequency based on eop signal or the SOF signal of usb host output.Described eop signal and SOF signal have minimum error, thereby can be used as the clock frequency adjustment foundation of the built-in clock generator of USB device.Thus, the present invention does not need in the USB device, quartz (controlled) oscillator to be set in addition, can effectively reduce costs.
Description of drawings
Differential wave frequency plot when Fig. 1 is the upper USB of USB device connection system.
Fig. 2 is the block diagram of the clock frequency regulating circuit of first embodiment of the invention.
Fig. 3 is the operation workflow figure of the clock frequency method of adjustment of first embodiment of the invention.
Fig. 4 is the block diagram of the clock frequency regulating circuit of second embodiment of the invention.
Fig. 5 is the external signal that receives of the phase detectors of Fig. 4 and the sequential chart of local signal.
Fig. 6 is another block diagram of the clock frequency regulating circuit of second embodiment of the invention.
Fig. 7 is the operation workflow figure of the clock frequency method of adjustment of second embodiment of the invention.
Description of reference numerals
Embodiment
In order to allow above and other objects of the present invention, feature and the advantage can be more obvious, hereinafter will coordinate appended diagram, be described in detail below.In explanation of the present invention, identical member is with identical symbolic representation, in this close first chat bright.
Please refer to shown in Figure 1ly, the differential wave sequential chart that it shows when the USB device of the embodiment of the present invention connects upper USB system comprises that the positive differential wave D+ of USB and USB minus tolerance move signal D-.In the connection initial stage, time t in figure for example
1-t
2During, the USB device can be received (reset) signal of resetting from the USB of USB interface.Then, every through an information frame time (frame interval time), that is to say 1 millisecond (ms), for example the t in figure
2-t
3, t
3-t
4... during, no matter whether carry out data transmission, the USB device all can continue to receive Keep Alive signal from USB interface (eop signal of low speed variator) or SOF signal (device at full speed); Speeder can be received the SOF signal in every 125 microseconds, and the present invention namely utilizes this signal as the reference signal of adjusting the clock generator in the USB device.
Please refer to shown in Figure 2ly, it shows the block diagram of clock frequency regulating circuit 10 of the clock generator of first embodiment of the invention, and wherein said clock frequency regulating circuit 10 is applicable to the USB device.Described clock frequency regulating circuit 10 comprises clock generator 11 and correcting unit 12.Described clock generator 11 is in order to producing the adjustable clock signal clk of frequency, and has output terminal 11a and input end 11b.Described clock generator 11 for example can be the RC oscillator, but is not limited to this.
Shown in Fig. 1 and 2, the clock signal clk frequency that described correcting unit 12 is produced to adjust described clock generator 11 in order to export control signal S, and comprise first input end 12a, the second input end 12b and signal output part 12c.The feedback signal of the clock signal clk that the described clock generator 11 of described first input end 12a reception produces; Described the second input end 12b receives the USB differential wave from the USB system.Described correcting unit 12 is according to each information frame time, for example t of described USB differential wave
2-t
3, t
3-t
4..., described clock signal clk is counted, and produced according to described count results the clock signal clk frequency that described control signal S is produced with the described clock generator 11 of relative adjustment.Described control signal S for example can be digital signal, and when described clock generator 11 was the RC oscillator, described control signal S can change R value, the C value in described clock generator 11 or change simultaneously the RC value.
In a kind of embodiment, suppose that the USB device is the full speed device, according to the data transmission standard of USB system, the frequency of described clock signal clk is for example 6 MHz (MHz), and the information frame time in the USB differential wave between every two SOF (start of frame) signal is 1 millisecond (ms), can set pre-set count values and be [1ms/ (1/6MHz)]=6000; And the tolerable error range of described clock signal clk frequency is ± 0.25%, namely described correcting unit 12 according to each information frame time of described USB differential wave, described clock signal clk is counted the pre-set count values of trying to achieve should be between 5985 and 6015.Due to the impact that is subject to processing procedure and operating environment, the clock signal clk that described clock generator 11 produces not is to be fixed as 6MHz, the count value of according to each information frame time of described USB differential wave, described clock signal clk being counted gained when described correcting unit 12 is lower than 5985 the time, represent that described clock signal clk frequency is too low, 12 of described correcting units produce the clock signal clk frequency that described control signal S is produced to improve described clock generator 11; Otherwise, higher than 6015 the time, representing that described clock signal clk frequency is too high when the count value of gained, 12 of described correcting units produce the clock signal clk frequency that described control signal S are produced to reduce described clock generator 11.Scrutablely be, described clock signal clk frequency is not defined as 6MHz, and it also can be the integral multiple of 6MHz, for example 12MHz, 18MHz, 24MHz..., and pre-set count values can be set according to different clock signal frequencies.
In addition, for hanging down speed variator, according to the data transmission standard of USB system, described clock signal clk frequency is for example 1.5MHz when the USB device, and the information frame time in the USB differential wave between every two Keep Alive signals is similarly 1 millisecond, and can to set pre-set count values be 1500; And the tolerable error range of described clock signal clk is ± 1.5%, and namely according to each information frame time of described USB differential wave, described clock signal clk to be counted the pre-set count values scope of trying to achieve be 1477.5 and 1522.5 to described correcting unit 12.Described correcting unit 12 judges whether described count value exceed described pre-set count values scope equally, and produce according to this described control signal S with the clock signal clk frequency of the described clock generator 11 of relative adjustment.
Please refer to shown in Fig. 2 and 3, Fig. 3 shows the process flow diagram of the clock frequency method of adjustment of first embodiment of the invention.At first, described clock generator 11 is by the adjustable clock signal clk of described output terminal 11a output frequency, and described clock signal clk feeds back to described correcting unit 12 via the first input end 12a of described correcting unit 12.Simultaneously, described correcting unit 12 is via the USB differential wave of described the second input end 12b reception from USB interface.Then, described correcting unit 12 was counted described clock signal clk according to each information frame time of described USB differential wave, and tried to achieve count value (step 121).Described correcting unit 12 judges that whether described count value is greater than first threshold, be for example 6015 (steps 122) in the full speed device, during greater than described first threshold, 12 of described correcting units produce the clock signal clk frequency (step 123) that control signal S are produced to reduce it to described clock generator 11 when described count value; Otherwise judge that then whether described count value is less than Second Threshold, be for example 5985 (steps 124) in the full speed device, during less than described Second Threshold, 12 of described correcting units produce the clock signal clk frequency (step 125) that control signal S are produced to improve it to described clock generator 11 when described count value; Otherwise keep the clock signal clk frequency (step 126) that described clock generator 11 produces.Then get back to step 121 repeatedly carrying out the counting of described clock signal clk, and adjust immediately when drift occurs described clock signal clk frequency, to keep the precision of the clock signal clk frequency that described clock generator 11 produced.Scrutablely be, step 122 and 123 with the order of step 124 and 125 can be opposite.
Please refer to shown in Figure 4, its show the clock frequency regulating circuit 10 of second embodiment of the invention ' block diagram, its comprise data sink 13, correcting unit 12 ' and frequency generating circuit 11 '.Described data sink 13 receives external signals, for example from the data stream of usb host, and output host signal S
H, it comprises initial (SOF) signal of information frame or EOP (end of packet, the end packet) signal of described data stream; That is described data sink 13 is in order to obtain out SOF signal or eop signal from described data stream.
Described correcting unit 12 ' comprise phase detectors 121 ' and control circuit 122 ', and have first input end 12a ', the second input end 12b ' and signal output part 12c '.Described phase detectors 121 ' from the host signal S of described the second input end 12b ' reception from described data sink 13
HAnd from described first input end 12a ' reception from described frequency generating circuit 11 ' local signal S
L, calculate and export described host signal S
HWith described local signal S
LPhase difference Ph
iDescribed control circuit 122 ' described phase difference Ph of reception
i, and from the clock signal clk of the described frequency generating circuit 11 of described first input end 12a ' reception ' generation, according to described clock signal clk counting Δ Ph
iCount value, and according to described count value from the clock frequency of described signal output part 12c ' output control signal S with the clock signal clk of adjusting described frequency generating circuit 11 ' generation.
Described frequency generating circuit 11 ' as the local oscillation circuit of USB device, it comprises clock generator, is preferably programmable oscillator (programmable oscillator) to produce described clock signal clk.Described frequency generating circuit 11 ' can adjust according to the control signal S that receives the clock frequency of described clock signal clk.Described frequency generating circuit 11 ' and feed back described clock signal clk to described control circuit 122 ' and output described local signal S
LTo described phase detectors 121 '.Described local signal S
LFrequency far below the clock frequency of described clock signal clk; In a kind of embodiment, described local signal S
LFor example can be the signal of described clock signal clk after frequency elimination and phase retardation, wherein the divisor of frequency elimination can determine according to clock frequency and the described data stream of described clock signal clk.
Please refer to shown in Figure 5ly, it shows the described host signal S of the described phase detectors 121 of Fig. 4 ' receive
HAnd described local signal S
LSequential chart, wherein said host signal S
HAnd described local signal S
LBetween have described phase difference Ph
i(e.g. Δ Ph
1-Δ Ph
3).Should be noted that, although the Ph of phase difference described in Fig. 5
iBe shown as described host signal S
HSOF signal (e.g.SOF1-SOF3) and described local signal S
LPulse (e.g.S
L1-S
L3) phase differential between rising edge, but the present invention is not limited to this.Described phase difference Ph
iAlso can be described host signal S
HSOF signal and described local signal S
LThe pulse negative edge or the phase differential between other pulse position.In addition, scrutablely be, in host signal S described in low speed variator
HComprise eop signal.
Combine it, the clock frequency regulating circuit 10 of the present embodiment ' obtain host signal S in external data stream by described data sink 13
H, for example SOF signal or eop signal; The described host signal S of described correcting unit 12 ' calculate
HWith local signal S
LBetween phase difference Ph
i, and count described phase difference Ph according to the present clock signal clk of described frequency generating circuit 11 ' export
iCount value, and according to described count value output control signal S with adjust or keep described frequency generating circuit 11 ' clock frequency; Wherein, as described local signal S
LWith described host signal S
HFrequency roughly the same (be described phase difference Ph
iBetween preset range) time, the clock signal clk that described frequency generating circuit 11 ' output is fixing; Yet, as described local signal S
LWith described host signal S
HPhase difference Ph
iWhen exceeding preset range, (for example the low speed USB interface is ± 1.5%, the USB interface is ± 0.25% at full speed, hi-speed USB interface is ± 0.05%), the clock frequency of the described frequency generating circuit 11 of described correcting unit 12 ' control ' described clock signal clk of adjustment.
Please refer to shown in Figure 6, its show the clock frequency regulating circuit 10 of second embodiment of the invention ' another schematic block diagram.Fig. 6 demonstrates other member of the frequency generating circuit 11 of Fig. 4 ' comprise; Namely, described frequency generating circuit 11 ' also comprise clock generator 11, frequency eliminator 111 ' and phase delay device 112 '.Described clock generator 11 is as the local oscillator of USB device, in order to produce described clock signal clk.Described clock signal clk as the local clock signal of described USB device and be fed back to simultaneously described correcting unit 12 ' control circuit 122 '.Described frequency eliminator 111 ' in order to described clock signal clk frequency elimination to roughly with described host signal S
HSOF signal or eop signal have same frequency.Described phase delay device 112 ' with signal S after frequency elimination
L' postpone to become described local signal S after preset phase
LWith input to described correcting unit 12 ' phase detectors 121 '.Described data sink 13 is also exported described host signal S
HTo described phase delay device 112 ' so that can described local signal S
LOutput, described preset phase is preset by system.In another embodiment, the described frequency generating circuit 11 of described frequency eliminator 111 ' and described phase delay device 112 ' can not be contained in ' in.
Please be simultaneously with reference to shown in Fig. 6 and 7, Fig. 7 show the clock frequency regulating circuit 10 of second embodiment of the invention ' the operation workflow figure of clock frequency method of adjustment.In the clock frequency method of adjustment of the present embodiment, the described host signal S of described control circuit 122 ' reception
HWith described local signal S
LBetween phase difference Ph
i, and according to the present clock frequency of described clock signal clk to described phase difference Ph
iCount value is counted (step S
21); Then, described control circuit 122 ' judge that whether described count value is greater than the 3rd threshold value TH3 (step S
22); When described count value greater than described the 3rd threshold value TH3, the clock frequency that represents described clock generator 11 is too slow, and therefore described control circuit 122 ' described control signal S of output improves clock frequency (the step S of described clock signal clk to control described clock generator 11
221); If not, described control circuit 122 ' judge that then whether described count value is less than the 4th threshold value TH4 (step S
23).When described count value less than described the 4th threshold value TH4, the clock frequency that represents described clock generator 11 is too fast, and therefore described control circuit 122 ' described control signal S of output reduces clock frequency (the step S of described clock signal clk to control described clock generator 11
231); If not, represent the clock frequency of described clock generator 11 between preset range, described control circuit 122 ' export described control signal S to keep clock frequency (the step S of described clock signal clk
24).Should be noted that, the frequency step (frequency step) that the described clock generator 11 of described control circuit 122 ' control improves and reduce clock frequency is according to the practical application decision, and there is no particular restriction.In addition, step S
22, S
221And step S
23, S
231Execution sequence be not defined as disclosed person in Fig. 7 yet, for example its order also can be opposite.In the present embodiment, described the 3rd threshold value TH3 is greater than described the 4th threshold value TH4.
Below enumerate an embodiment clock frequency method of adjustment of the present invention be described, and this to sentence hi-speed USB interface be that example describes.In hi-speed USB interface, the initial clock signal clk of described clock generator 11 outputs for example is positioned near 48MHz (making it herein is f1), and clock frequency method of adjustment of the present invention is being proofreaied and correct the initial clock frequency (being f1) of described clock signal clk for being substantially equal to 48MHz; Signal S after the frequency elimination after described frequency eliminator 111 ' frequency elimination
L' be (for example to be f1/n) near 1k, wherein n is the divisor of frequency elimination; For example, if the host signal S of described data sink 13 outputs
HBe 1k, divisor n is 48000 herein.Described the 3rd threshold value and the 4th threshold value can be respectively 48MHz ± 0.05% * 48MHz.Scrutable is that the clock frequency of described clock signal clk, divisor n and threshold value determine according to different application, are not limited to above-mentioned count value.
Please be simultaneously with reference to Fig. 5 to 7, when described phase delay device 112 ' (the SOF1 rising edge for example detected) when receiving first SOF signal, the present clock frequency (being f1) according to described clock signal clk postpones pre-set count values (for example 24000 countings) to export described local signal S
LTo described phase detectors 121 ', namely SOF1 is also available with activation S
L1Output.Described phase detectors 121 ' calculate SOF1 and described local signal S
LFirst pulse S
L1Phase difference Ph
1, and with described phase difference Ph
1Be sent to described control circuit 122 ', this moment described phase difference Ph
1As the reference phase differential.
Described control circuit 122 ' according to the present clock frequency (being f1) of described clock signal clk is to described phase difference Ph
1Count value is counted (step S
21), this moment, count value was 24000, between between described the 3rd threshold value TH3 and described the 4th threshold value TH4, so described control circuit 122 ' do not adjust present clock frequency f1 (step S of described clock generator 11
24), so described frequency generating circuit 11 ' continue with frequency f 1/n output local signal S
LIn this embodiment, the permissible error of the clock frequency of clock generator 11 should be situated between ± 0.05% in, namely described the 3rd threshold value TH3=24012 and described the 4th threshold value TH4=23088.
Then, described phase detectors 121 ' receive second SOF signal (for example SOF2) and described local signal S
LNext pulse S
L2And calculate phase difference Ph
2, and with described phase difference Ph
2Be sent to described control circuit 122 '.Described control circuit 122 ' according to the present clock frequency (being f1) of described clock signal clk is to described phase difference Ph
2Count value is counted (step S
21), and more described count value and described the 3rd threshold value TH3 and described the 4th threshold value TH4.
When described count value is still between between described the 3rd threshold value TH3 and described the 4th threshold value TH4, described control circuit 122 ' still do not adjust present clock frequency f1 (the step S of described clock generator 11
24), so described frequency generating circuit 11 ' continue with frequency f 1/n output local signal S
LThen get back to step S
21, that is to say described control circuit 122 ' still according to the present clock frequency (being f1) of described clock signal clk to next phase difference Ph
3Count count value, and determine whether to adjust the present clock frequency f1 of described clock generator 11 according to described count value.
In addition, as described count value (step S during greater than described the 3rd threshold value TH3
22), the clock frequency that the described clock generator 11 of described control circuit 122 ' control improves its clock signal clks is f2 (step S
221), this moment, described frequency generating circuit 11 ' change was with frequency f 2/n output local signal S
LWhen described phase delay device 112 ' (the SOF3 rising edge for example detected) when receiving next SOF signal, the present clock frequency (being f2) according to described clock signal clk postpones pre-set count values (for example 24000 countings) to export described local signal S
LTo described phase detectors 121 '.Described phase detectors 121 ' calculate SOF3 and described local signal S
LNext pulse S
L3Phase difference Ph
3And transmit described phase difference Ph
3To described control circuit 122 ', this moment described phase difference Ph
3Poor as a new fixed phase.Program is then got back to step S
21According to follow-up host signal S
HSOF signal and local signal S
LBetween the present clock frequency f2 of the described clock generator 11 of adjusting offset.
In addition, as described count value (step S during less than described the 4th threshold value TH4
23), the clock frequency that the described clock generator 11 of described control circuit 122 ' control reduces its clock signal clks is f3 (step S
231), this moment, described frequency generating circuit 11 ' change was with frequency f 3/n output local signal S
LWhen described phase delay device 112 ' (the SOF3 rising edge for example detected) when receiving next SOF signal, the present clock frequency (being f3) according to described clock signal clk postpones a pre-set count values (for example 24000 countings) to export described local signal S
LTo described phase detectors 121 '.Described phase detectors 121 ' calculate SOF3 and described local signal S
LNext pulse S
L3Phase difference Ph
3And transmit described phase difference Ph
3To described control circuit 122 ', this moment described phase difference Ph
3Poor as a new fixed phase.Program is then got back to step S
21According to follow-up host signal S
HSOF signal and local signal S
LBetween the present clock frequency f3 of the described clock generator 11 of adjusting offset.
As mentioned above, in known technology, owing to quartz (controlled) oscillator being set to increase the mode of oscillation frequency degree of accuracy in the chip by the USB device, can increase the complexity of cost and application circuit.The present invention is only by arranging the adjustable clock generator of frequency in the chip of USB device, and take the eop signal of USB differential wave or SOF signal as benchmark, dynamically adjust the clock signal frequency that clock generator produces, increase thus the frequency accuracy and reduce costs.
Although the present invention is open with previous embodiment, so it is not to limit the present invention, any the technical staff in the technical field of the invention, without departing from the spirit and scope of the present invention, when making various changes or modifications.Therefore protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (20)
1. clock frequency regulating circuit, this clock frequency regulating circuit comprises:
Frequency generating circuit, clock signal and local signal;
Data sink receives usb data and flows and export host signal, and described host signal comprises SOF signal or eop signal; And
Correcting unit, receive described host signal and described local signal, according to the described host signal of described clock signal counting with the count value of the phase differential of described local signal and according to the described clock signal of described count value adjustment.
2. clock frequency regulating circuit according to claim 1, wherein said correcting unit judge that also described count value whether between preset range, adjusts or keep the clock frequency of described clock signal thus.
3. clock frequency regulating circuit according to claim 2, wherein,
When described correcting unit judges described count value greater than the 3rd threshold value, improve described clock frequency;
When described correcting unit judges described count value less than the 4th threshold value, reduce described clock frequency; And
When the described count value of described correcting unit judgement is between described the 3rd threshold value and described the 4th threshold value, keep described clock frequency; Wherein said the 3rd threshold value is greater than described the 4th threshold value.
4. clock frequency regulating circuit according to claim 1, wherein said local signal is the signal of described clock signal after frequency elimination and phase retardation.
5. clock frequency regulating circuit according to claim 1, wherein said frequency generating circuit also comprises clock generator, frequency eliminator and phase delay device; Described clock generator produces described clock signal and feeds back described clock signal to described correcting unit; Described frequency eliminator to described clock signal frequency elimination to produce signal after frequency elimination; After described phase delay device postpones described frequency elimination, signal is to export described local signal to described correcting unit.
6. clock frequency regulating circuit according to claim 1, wherein said frequency generating circuit also receive described host signal so that output that can described local signal from described data sink.
7. clock frequency regulating circuit according to claim 1, wherein said correcting unit also comprises phase detectors and control circuit; Described phase detectors receive described host signal and described local signal and export described phase differential; Described control circuit is counted the described count value of described phase differential according to described clock signal, and adjusts described clock signal according to described count value.
8. clock frequency regulating circuit according to claim 7, wherein said frequency generating circuit also comprises clock generator, frequency eliminator and phase delay device; Described clock generator produces described clock signal and feeds back described clock signal to described control circuit; Described frequency eliminator to described clock signal frequency elimination to produce signal after frequency elimination; After described phase delay device postpones described frequency elimination, signal is to export described local signal to described phase detectors.
9. the clock frequency method of adjustment of a clock frequency regulating circuit, described clock frequency regulating circuit comprises frequency generating circuit, correcting unit and data sink, and described clock frequency method of adjustment comprises the following step:
Receiving usb data by described data sink flows and produces host signal;
Produce local signal and clock signal by described frequency generating circuit;
Receive described local signal and described host signal calculating phase differential by described correcting unit, and according to the count value of the described phase differential of described clock signal counting; And
Adjust the clock frequency of described clock signal according to described count value.
10. clock frequency method of adjustment according to claim 9, the wherein said step of adjusting the clock frequency of described clock signal according to described count value also comprises: whether judge described count value between preset range, adjust thus or keep the described clock frequency of described clock signal.
11. clock frequency method of adjustment according to claim 10, this clock frequency method of adjustment also comprises the following step:
During greater than the 3rd threshold value, improve described clock frequency when described count value;
During less than the 4th threshold value, reduce described clock frequency when described count value; And
When described count value is between described the 3rd threshold value and described the 4th threshold value, keep described clock frequency.
12. clock frequency method of adjustment according to claim 10, wherein said preset range be pre-set count values ± 0.05%, ± 0.25% or ± 1.5% described pre-set count values.
13. clock frequency method of adjustment according to claim 9, this clock frequency method of adjustment also comprises the following step:
By described frequency generating circuit to described clock signal frequency elimination to produce signal after frequency elimination; And
After postponing described frequency elimination by described frequency generating circuit, signal is to produce described local signal.
14. clock frequency method of adjustment according to claim 9, this clock frequency method of adjustment also comprises the following step: receive described host signal so that can the described local signal of described frequency generating circuit output by described frequency generating circuit.
15. the clock frequency method of adjustment of a clock frequency regulating circuit, described clock frequency regulating circuit comprises clock generator, frequency eliminator, phase delay device, phase detectors, control circuit and data sink, and described clock frequency method of adjustment comprises the following step:
Receiving usb data by described data sink flows and produces host signal;
Produce adjustable clock signal by described clock generator;
By described frequency eliminator to described adjustable clock signal frequency elimination to produce signal after frequency elimination;
By described phase delay device to described frequency elimination after signal carry out preset phase delay to produce local signal;
Receive described host signal and described local signal to calculate phase differential by described phase detectors; And
Receive described phase differential, count the count value of described phase differential and control described clock generator according to described count value according to described adjustable clock signal by described control circuit.
16. clock frequency method of adjustment according to claim 15, this clock frequency method of adjustment also comprises: receive described host signal so that the output of the described local signal of energy with described phase delay device from described data sink.
17. clock frequency method of adjustment according to claim 15, in wherein said step according to the described clock generator of described count value control, described control circuit judges that described count value whether between preset range, adjusts or keep the clock frequency of described clock generator thus.
18. clock frequency method of adjustment according to claim 17, this clock frequency method of adjustment also comprises the following step:
During greater than the 3rd threshold value, improve described clock frequency when described count value;
During less than the 4th threshold value, reduce described clock frequency when described count value; And
When described count value is between described the 3rd threshold value and described the 4th threshold value, keep described clock frequency; Wherein said the 3rd threshold value is greater than described the 4th threshold value.
19. clock frequency method of adjustment according to claim 15, wherein said preset phase is determined by described clock frequency vibration pre-set count values.
20. clock frequency method of adjustment according to claim 15, wherein said host signal comprises SOF signal or eop signal.
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| CN 201110343302 CN103092256A (en) | 2011-11-03 | 2011-11-03 | Clock frequency adjusting circuit and clock frequency adjusting method thereof |
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| CN 201110343302 CN103092256A (en) | 2011-11-03 | 2011-11-03 | Clock frequency adjusting circuit and clock frequency adjusting method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103312325A (en) * | 2013-06-26 | 2013-09-18 | 龙迅半导体科技(合肥)有限公司 | Frequency synthesizer |
| CN103996388A (en) * | 2014-05-04 | 2014-08-20 | 京东方科技集团股份有限公司 | Signal correction method and signal correction device |
| CN106201956A (en) * | 2015-05-08 | 2016-12-07 | 伟诠电子股份有限公司 | Apparatus and method for automatically correcting clock of amorphous oscillator |
| CN107968648A (en) * | 2017-11-17 | 2018-04-27 | 珠海亿智电子科技有限公司 | A kind of system of the calibration without crystal oscillator USB device internal oscillator clock |
| CN109426136A (en) * | 2017-08-29 | 2019-03-05 | 精工爱普生株式会社 | Time-to-digital conversion circuit, circuit device, physical amount measuring device, electronic equipment and moving body |
| CN113076278A (en) * | 2021-04-02 | 2021-07-06 | 深圳市航顺芯片技术研发有限公司 | USB device clock calibration method, device, system and computer readable storage medium |
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- 2011-11-03 CN CN 201110343302 patent/CN103092256A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103312325A (en) * | 2013-06-26 | 2013-09-18 | 龙迅半导体科技(合肥)有限公司 | Frequency synthesizer |
| CN103312325B (en) * | 2013-06-26 | 2016-08-24 | 龙迅半导体（合肥）股份有限公司 | A kind of frequency synthesizer |
| CN103996388A (en) * | 2014-05-04 | 2014-08-20 | 京东方科技集团股份有限公司 | Signal correction method and signal correction device |
| CN103996388B (en) * | 2014-05-04 | 2016-07-06 | 京东方科技集团股份有限公司 | Signal calibration method and signal correction device |
| US9524692B2 (en) | 2014-05-04 | 2016-12-20 | Boe Technology Group Co., Ltd. | Signal correcting method and signal correcting device |
| CN106201956A (en) * | 2015-05-08 | 2016-12-07 | 伟诠电子股份有限公司 | Apparatus and method for automatically correcting clock of amorphous oscillator |
| CN106201956B (en) * | 2015-05-08 | 2021-04-06 | 伟诠电子股份有限公司 | Apparatus and method for automatically correcting clock of amorphous oscillator |
| CN109426136A (en) * | 2017-08-29 | 2019-03-05 | 精工爱普生株式会社 | Time-to-digital conversion circuit, circuit device, physical amount measuring device, electronic equipment and moving body |
| CN109426136B (en) * | 2017-08-29 | 2021-07-30 | 精工爱普生株式会社 | Time-to-digital conversion circuit, circuit device, physical quantity measuring device, electronic apparatus, and moving object |
| CN107968648A (en) * | 2017-11-17 | 2018-04-27 | 珠海亿智电子科技有限公司 | A kind of system of the calibration without crystal oscillator USB device internal oscillator clock |
| CN113076278A (en) * | 2021-04-02 | 2021-07-06 | 深圳市航顺芯片技术研发有限公司 | USB device clock calibration method, device, system and computer readable storage medium |
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Application publication date: 20130508 |