CN107968648A - A kind of system of the calibration without crystal oscillator USB device internal oscillator clock - Google Patents
A kind of system of the calibration without crystal oscillator USB device internal oscillator clock Download PDFInfo
- Publication number
- CN107968648A CN107968648A CN201711143486.4A CN201711143486A CN107968648A CN 107968648 A CN107968648 A CN 107968648A CN 201711143486 A CN201711143486 A CN 201711143486A CN 107968648 A CN107968648 A CN 107968648A
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- Prior art keywords
- oscillator
- clock
- sof
- coarse adjustment
- usb
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/0805—Details of the phase-locked loop the loop being adapted to provide an additional control signal for use outside the loop
Abstract
The invention discloses a kind of system of the calibration without crystal oscillator USB device internal oscillator clock, which includes：Coarse adjustment alignment loop, fine tuning alignment loop.Wherein, coarse adjustment alignment loop includes oscillator, phaselocked loop, counter, the first counting decision device, eFuse, coarse adjustment control word selector, it utilizes chip CP（Chip Probe）The reference clock filled outside test phase calibrates roughly the clock that oscillator produces, to ensure that USB device can identify the SOF in the data flow that usb host sends over（Strat Of Frame）Token packet.Fine tuning alignment loop includes oscillator, phaselocked loop, SOF detectors, SOF interval counters, the second counting decision device, SOF pulse signals in the data flow that the usb host that it is detected using SOF detectors sends over carry out fine adjustment as the clock that reference clock produces oscillator, to ensure to reach the frequency deviation of usb protocol requirement, so as to achieve the purpose that saving chip exterior has source crystal oscillator or crystal.
Description
Technical field
The present invention relates to serial interface data transmission technique field, more particularly to the USB of no crystal oscillator（Universal
Serial Bus）Equipment internal oscillator clock alignment system.
Background technology
USB2.0 agreements have stringent limitation to the work frequency deviation between USB hosts, USB equipment, for example, low speed passes
Defeated pattern requires frequency deviation to be less than 1.5M ± 1.5%（15000ppm）, full speed transfer pattern require frequency deviation be less than 12M ± 0.25%
（2500ppm）, high speed transmission mode require frequency deviation be less than 480M ± 0.05%（500ppm）.Therefore, in traditional USB interface number
It is full as shown in Figure 1, except usb host 100, USB device 101 and the usb bus 104 between them according in transmission architecture
Between sufficient usb host and equipment frequency deviation requirement, usb host 100, USB device 101 be respectively adopted high-precision crystal oscillator 102,
103 are used as reference clock source.However, use the high-precision external PCB surface for having source crystal oscillator or crystal is of high cost, occupancy is larger
Product, and fixed difference on the frequency is had between USB hosts and equipment.
In consideration of it, it is necessary an internal oscillator, such as a RC built in the reference clock source of USB equipment, will to be designed
（Resister Capacitor）Oscillator, the reference clock source as USB equipment.However, due to the deviation of technique, RC shakes
Swing device output clock frequency deviation and be up to ± 25%, can not ensure that USB device can identify usb host when being just connected with usb host
The handshake packet sended over, particularly USB2.0 fast modes, it is likely that connection failure.If carry out CP in chip（Chip
Probe）Test phase, certain voltage, at a temperature of, oscillator is calibrated using the reference clock of outer filling, by calibration value
EFuse storages are write, also can only calibration process deviation.Oscillator output clock frequency is with supply voltage, temperature built in actual product
Degree change can still exceed the requirement of USB2.0 fast modes frequency deviation, cause USB2.0 equipment to be connected into USB2.0 hosts
Work(, but subsequent data transmission is likely to interrupt.
The content of the invention
It is an object of the invention to provide a kind of system for calibrating the USB equipment internal oscillator clocks without crystal oscillator.
A kind of clock alignment system, including coarse adjustment, the calibration of two synchronizing frequency of fine tuning, both possess different frequency calibration scopes
And precision.
First step coarse adjustment, in the CP of chip（Chip Probe）Test phase, sets USB using the reference clock of outer filling
The clock that standby internal oscillator produces is calibrated roughly（Calibration process deviation）, it is ensured that USB equipment is just connected to usb host
When, it can identify the SOF in the data flow that USB hosts send over（Strat Of Frame）Token packet.
Second step fine tuning, the SOF pulse signals to detect produce USB equipment internal oscillator as reference clock
Clock carry out fine adjustment（Real time calibration, calibration process, power supply, temperature deviation）, to ensure to reach USB2.0 protocol definitions
Frequency deviation requirement, so as to achieve the purpose that saving chip exterior has source crystal oscillator or crystal.
In one of the embodiments, a kind of clock alignment system, including two coarse adjustment, fine tuning alignment loops.Wherein, slightly
Alignment loop is adjusted to include oscillator, phaselocked loop, counter, the first counting decision device, eFuse, coarse adjustment control word selector.Fine tuning
Alignment loop includes oscillator, phaselocked loop, SOF detectors, SOF interval counters, the second counting decision device.
The coarse adjustment alignment loop shares the oscillator and the phaselocked loop with the fine tuning alignment loop.
In the coarse adjustment alignment loop, the oscillator output clock gives the phaselocked loop and carries out frequency multiplication, described
Phaselocked loop output clock gives the counter and the reference clock cycle filled outside the CP stages is counted, and the counter counts
Value is given the first counting decision device and is made decisions, and the first counting decision device court verdict is sent to the eFuse respectively
When being sent to the oscillator with the coarse adjustment control word selector, the coarse adjustment control word selector output control word it exported
Clock frequency carries out coarse adjustment.When the described first counting decision device judgement does not lock, the coarse adjustment control word selector directly selects
Select described first and count decision device output control word, continue to carry out coarse adjustment to the oscillator.When the described first counting decision device
During judgement locking, the control word for being sent to the eFuse writes the Efuse, the coarse adjustment alignment loop locking, the coarse adjustment control
Word selector processed selects the control word stored in the eFuse, completes the coarse adjustment to the oscillator.
In the fine tuning alignment loop, the oscillator output clock gives the phaselocked loop and carries out frequency multiplication, described
Phaselocked loop output clock gives the SOF detectors, the SOF interval counters respectively, what the SOF detectors detected
SOF pulse signals give the SOF interval counters, it are counted by phaselocked loop output clock, count value is given
The second counting decision device makes decisions, and the second counting decision device output control word is sent to the oscillator and it is exported
Clock frequency carries out fine tuning.When the described second counting decision device judgement does not lock, described second counts decision device output control
Word processed continues to carry out coarse adjustment to the oscillator.When described second counts decision device judgement locking, described second counts judgement
Device output control letter lock is determined, and completes the fine tuning to the oscillator.
Brief description of the drawings
The present invention is specifically described below with reference to attached drawing and with reference to example, is realized with system the advantages of the method for the present invention
Mode will be more obvious and clear, and wherein content is only used for explanation of the present invention shown in attached drawing, without forming to this
Invention in all senses on limitation, in the accompanying drawings：
Fig. 1 is traditional USB interface data transmission architecture schematic diagram；
Fig. 2 is the USB interface data transmission architecture schematic diagram using the clock alignment system of present invention；
Fig. 3 is the USB device internal oscillator clock alignment system schematic of invention；
Fig. 4 is the frame period schematic diagram of full speed USB device；
Fig. 5 is the frame period schematic diagram of high-speed USB device.
Embodiment
Fig. 2 is the USB interface data transfer frame using the USB device internal oscillator clock alignment system of present invention
Structure, USB equipment 201 include internal oscillator clock alignment system 203.
As shown in figure 3, in a specific embodiment, the USB equipment internal oscillator clock alignment systems
203, including coarse adjustment alignment loop 310 and fine tuning alignment loop 320, their shared oscillators 301 and phaselocked loop 302.
As shown in figure 3, in one embodiment, coarse adjustment alignment loop 310 includes oscillator 301, phaselocked loop 302, meter
Number device 311, first counts decision device 312, eFuse314, coarse adjustment control word selector 313.Oscillator 301 exports clock and gives
Phaselocked loop 302 doubles, and phaselocked loop 302 exports clock 315 and gives counter 311, to the base filled outside chip CP test phases
The a cycle of punctual clock 305 is counted, and the count value of counter 311 is given the first counting decision device 312 and made decisions, when
Count value is more than NdnOr less than NupWhen, coarse adjustment control word selector 313 directly selects the control of the first counting decision device 312 output
Word processed, coarse adjustment is carried out to oscillator 301.When count value is in Ndn1 、Nup1Between when, first count decision device 312 judgement locking,
Output control word 317 writes eFuse314, locking signal 316 puts height, and coarse adjustment control word selector 313 selects eFuse314 storages
Coarse adjustment control word, complete the coarse adjustment to oscillator 301.Corresponding phaselocked loop 302 exports the precision of clock 315,324,325,304
For 480MHz ± 2100ppm（Fast mode）、48MHz±10500ppm（Full-Speed mode）, it can be ensured that fine tuning alignment loop 320
In SOF detectors 321 correctly identify SOF token packets in the data flow that USB hosts send over.
In one of the embodiments, 305 frequency of reference clock is 0.25MHz.
In one of the embodiments, the count value Ndn1And Nup1, it is in high speed mode Ndn1=1924、Nup1=
1916, it is N under Full-Speed modedn1=194、Nup1=190。
As shown in figure 3, in one embodiment, fine tuning alignment loop 320 includes oscillator 301, phaselocked loop 302, SOF
Detector 321, SOF interval counters 322, second count decision device 323.Oscillator 301 export clock give phaselocked loop 302 into
Row multiplication, phaselocked loop 302 export clock 324 and give SOF detectors 321, and phaselocked loop 302 exports clock 325 and gives between SOF at the same time
Every counter 322, the SOF pulse signals that SOF detectors 321 detect give SOF interval counters 322, SOF interval counters
322 count results are given the second counting decision device 323 and are made decisions, and court verdict carries out fine tuning to oscillator 301.
Since the SOF token packets that USB hosts are sent to USB equipment are 1ms ± 500ns, high speed mould under Full-Speed mode
At intervals of 125us ± 62.5ns under formula, as shown in Figure 4,5.When the meter of the SOF interval counters 322 in fine tuning alignment loop 320
Numerical value, more than Ndn2Or less than Nup2When, second, which counts 323 output control word of decision device, continues the output clock progress of oscillator 301
Adjustment.When the count value of SOF interval counters 322, in Ndn2And Nup2Between when, fine tuning alignment loop 320 locks, second count
Decision device 323 exports coarse control word locking, and it is 480MHz that corresponding phaselocked loop 302, which exports 315,324,325,304 precision of clock,
±500ppm（Fast mode）、48MHz±2500ppm（Full-Speed mode）.
In one of the embodiments, the count value Ndn2And Nup2, it is in high speed mode Ndn2=60030、Nup2=
59970, it is N under Full-Speed modedn2=48120、Nup2=47880。
Above example is only the preferred example of the present invention, and design concept of the invention is not limited thereto, all at this
Within the spirit and principle of invention, any modification, equivalent replacement, improvement and so on, should be included in the protection model of the present invention
Within enclosing.
Claims (6)
1. a kind of system of the calibration without crystal oscillator USB device internal oscillator clock, it is characterised in that including coarse adjustment, two step of fine tuning
Frequency calibration, both possess different frequency calibration scope and precision.
2. clock alignment system according to claim 1, it is characterised in that first step coarse adjustment, in the CP of chip（Chip
Probe）Test phase, the clock produced using the reference clock of outer filling to USB equipment internal oscillator are calibrated roughly
（Calibration process deviation）, it is ensured that when USB equipment has just been connected to usb host, it can identify the data flow that USB hosts send over
In SOF（Strat Of Frame）Token packet.
3. clock alignment system according to claim 2, it is characterised in that second step fine tuning, with the SOF pulses detected
Signal carries out fine adjustment as the clock that reference clock produces USB equipment internal oscillator（Real time calibration, calibration process,
Power supply, temperature deviation）, to ensure the frequency deviation requirement for reaching USB2.0 protocol definitions, the active crystalline substance of chip exterior is saved so as to reach
Shake or the purpose of crystal.
4. a kind of system of the calibration without crystal oscillator USB device internal oscillator clock, it is characterised in that including coarse adjustment, fine tuning two
Alignment loop.
5. clock alignment system according to claim 4, it is characterised in that coarse adjustment alignment loop includes oscillator, lock phase
Ring, counter, first count decision device, eFuse, coarse adjustment control word selector；Oscillator output clock gives phaselocked loop progress
Multiplication, phaselocked loop output clock are given counter, the reference clock cycle filled outside the stage are counted, count value gives first
Decision device judgement is counted, court verdict is sent to eFuse and coarse adjustment control word selector, the output control of coarse adjustment control word selector respectively
Oscillator processed carries out frequency coarse adjustment.
6. clock alignment system according to claim 4, it is characterised in that fine tuning alignment loop includes oscillator, lock phase
Ring, SOF detectors, SOF interval counters, second count decision device；Oscillator output clock gives phaselocked loop and doubles, and locks
Phase ring output clock gives SOF detectors and SOF interval counters, and SOF interval counters detect SOF detectors
SOF pulse signals are counted, and count value gives the judgement of the second counting decision device, and output coarse control word control oscillator carries out
Frequency fine tuning.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711143486.4A CN107968648A (en) | 2017-11-17 | 2017-11-17 | A kind of system of the calibration without crystal oscillator USB device internal oscillator clock |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201711143486.4A CN107968648A (en) | 2017-11-17 | 2017-11-17 | A kind of system of the calibration without crystal oscillator USB device internal oscillator clock |
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Cited By (7)
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|---|---|---|---|---|
| CN109687867A (en) * | 2018-11-30 | 2019-04-26 | 珠海慧联科技有限公司 | A kind of no crystal oscillator USB device clock correcting method and calibration circuit |
| CN110113045A (en) * | 2019-05-20 | 2019-08-09 | 长沙景美集成电路设计有限公司 | It is a kind of applied to USB from the high-precision of equipment without crystal self-correcting clock system |
| CN110109643A (en) * | 2019-03-14 | 2019-08-09 | 恒玄科技（上海）有限公司 | A kind of the usb audio terminal system on chip and synchronous clock calibrating method of no crystal oscillator |
| CN110233620A (en) * | 2019-06-05 | 2019-09-13 | 长沙景美集成电路设计有限公司 | It is a kind of applied to USB from the Self-Tuning Algorithm of equipment clock system |
| CN112015691A (en) * | 2020-08-20 | 2020-12-01 | 中国科学院微电子研究所 | Clock calibration method and calibration circuit of serial bus equipment and electronic equipment |
| CN112398471A (en) * | 2019-08-12 | 2021-02-23 | 瑞昱半导体股份有限公司 | High-speed high-resolution digitally controlled oscillator and method thereof |
| CN114968889A (en) * | 2022-03-31 | 2022-08-30 | 珠海泰芯半导体有限公司 | High-speed USB sampling method and system |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109687867A (en) * | 2018-11-30 | 2019-04-26 | 珠海慧联科技有限公司 | A kind of no crystal oscillator USB device clock correcting method and calibration circuit |
| CN109687867B (en) * | 2018-11-30 | 2023-04-07 | 珠海慧联科技有限公司 | Clock calibration method and calibration circuit for crystal-oscillator-free USB (universal serial bus) equipment |
| CN110109643A (en) * | 2019-03-14 | 2019-08-09 | 恒玄科技（上海）有限公司 | A kind of the usb audio terminal system on chip and synchronous clock calibrating method of no crystal oscillator |
| CN110109643B (en) * | 2019-03-14 | 2022-09-23 | 恒玄科技(上海)股份有限公司 | Crystal-oscillator-free USB audio terminal on-chip system and synchronous clock calibration method |
| CN110113045A (en) * | 2019-05-20 | 2019-08-09 | 长沙景美集成电路设计有限公司 | It is a kind of applied to USB from the high-precision of equipment without crystal self-correcting clock system |
| CN110113045B (en) * | 2019-05-20 | 2023-11-14 | 长沙景美集成电路设计有限公司 | High-precision crystal-free self-correction clock system applied to USB slave equipment |
| CN110233620A (en) * | 2019-06-05 | 2019-09-13 | 长沙景美集成电路设计有限公司 | It is a kind of applied to USB from the Self-Tuning Algorithm of equipment clock system |
| CN110233620B (en) * | 2019-06-05 | 2023-09-22 | 长沙景美集成电路设计有限公司 | Self-correction algorithm applied to clock system of USB slave device |
| CN112398471A (en) * | 2019-08-12 | 2021-02-23 | 瑞昱半导体股份有限公司 | High-speed high-resolution digitally controlled oscillator and method thereof |
| CN112015691A (en) * | 2020-08-20 | 2020-12-01 | 中国科学院微电子研究所 | Clock calibration method and calibration circuit of serial bus equipment and electronic equipment |
| CN112015691B (en) * | 2020-08-20 | 2022-02-08 | 中国科学院微电子研究所 | Clock calibration method and calibration circuit of serial bus equipment and electronic equipment |
| CN114968889A (en) * | 2022-03-31 | 2022-08-30 | 珠海泰芯半导体有限公司 | High-speed USB sampling method and system |
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