CN107797442B - Time-to-digital conversion device and digital phase-locked loop - Google Patents
Time-to-digital conversion device and digital phase-locked loop Download PDFInfo
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- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
The invention is suitable for the technical field of accurate time measurement, and provides a time-to-digital conversion device and a digital phase-locked loop, wherein the device comprises: a power supply control circuit, a first delay circuit, a second delay circuit, and a time detection circuit; the power supply control circuit generates a first voltage and a second voltage and respectively transmits the first voltage and the second voltage to the first delay circuit and the second delay circuit; the first delay circuit delays the received first clock signal according to the first voltage; the second delay circuit delays the received second clock signal according to the second voltage; and the time detection circuit is used for receiving the first clock signal and the second clock signal which are subjected to delay processing and detecting the time difference between the first clock signal and the second clock signal. The device realizes the difference of two delays by inputting different voltages to the two delay circuits, thereby obtaining higher and more stable measurement precision and simultaneously reducing the requirements on the circuit process and layout.
Description
Technical Field
The invention belongs to the technical field of time accurate measurement, and particularly relates to a time digital conversion device and a digital phase-locked loop.
Background
With the advantages of small area and low power consumption of the chip technology, the full digital phase-locked loop gradually replaces the traditional phase-locked loop. The time-digital conversion device is used for detecting the phase difference between the output frequency and the reference frequency in the all-digital phase-locked loop. The detection of the phase difference is closely related to the detection of the time difference between the signals, and the accuracy of the time-to-digital conversion device determines the frequency accuracy achievable by the all-digital phase-locked loop.
At present, a common time-to-digital conversion device makes unit delay on an oscillator clock signal by setting a delay unit, and then calculates the time difference between the oscillator clock signal and a reference clock signal by a trigger. However, such a time-to-digital conversion device is greatly affected by the process of the circuit, for example: at nodes above the 90nm process, the minimum delay of 20ps can be realized; and at the process node below 90nm, the delay of 10 ps-20 ps can be realized. In the time-to-digital conversion device of the vernier caliper structure, the clock signal of the oscillator and the reference clock signal are respectively transmitted through a delay unit, and the time difference between the clock signal of the oscillator and the reference clock signal is calculated through a trigger, so that higher time measurement precision can be realized. However, the time-to-digital conversion device with the vernier caliper structure has high requirements on the process and layout matching of the circuit.
Disclosure of Invention
In view of the above, the embodiment of the invention provides a time-to-digital conversion device and a digital phase-locked loop, so as to solve the problems of low time measurement precision of the time-to-digital conversion device and high requirements on the process and layout matching of a circuit in the prior art.
A first aspect of an embodiment of the present invention provides a time-to-digital conversion apparatus, including: a power supply control circuit, a first delay circuit, a second delay circuit, and a time detection circuit;
the power supply control circuit is provided with a first voltage output end and a second voltage output end, the first voltage output end is connected with the first delay circuit, and the second voltage output end is connected with the second delay circuit; the power supply control circuit is used for generating a first voltage and a second voltage, and outputting the first voltage and the second voltage to the first delay circuit and the second delay circuit respectively through the first voltage output end and the second voltage output end;
a first delay circuit for receiving a first clock signal and performing delay processing on the first clock signal according to the first voltage;
the second delay circuit is used for receiving a second clock signal and carrying out delay processing on the second clock signal according to the second voltage;
and the time detection circuit is used for receiving the first clock signal and the second clock signal which are subjected to delay processing and detecting the time difference between the first clock signal and the second clock signal.
Optionally, the first delay circuit includes a plurality of first delay units, and the second delay circuit includes a plurality of second delay units, and a circuit structure of each of the first delay units is the same as a circuit structure of each of the second delay units.
Optionally, the first delay unit is an inverter or a buffer.
Optionally, the power supply control circuit includes:
a power supply;
the voltage dividing circuit is provided with an input end, a first output end and a second output end, wherein the input end is connected with the power supply, and the first output end and the second output end output different voltages;
the positive electrode of the first linear voltage stabilizer is connected with the first output end of the voltage dividing circuit, the negative electrode of the first linear voltage stabilizer is connected with the output end, and the output end of the first linear voltage stabilizer is also connected with the first delay circuit;
and the positive electrode of the second linear voltage stabilizer is connected with the second output end of the voltage dividing circuit, the negative electrode of the second linear voltage stabilizer is connected with the output end, and the output end of the second linear voltage stabilizer is also connected with the second delay circuit.
Optionally, the time detection circuit includes:
the data end of the Nth trigger is connected with the Nth node of the first delay circuit, and the clock control end of the Nth trigger is connected with the Nth node of the second delay circuit; wherein N is a positive integer.
Optionally, the first clock signal is an oscillator clock signal, and the second clock signal is a reference clock signal.
A second aspect of an embodiment of the present invention provides a digital phase locked loop, including a digital loop filter, an oscillator, and a time-to-digital conversion device as described in any one of the above; the time-to-digital conversion device is connected with the digital loop filter, the digital loop filter is connected with the oscillator, and the oscillator is also connected with the time-to-digital conversion device;
the oscillator is used for outputting an oscillator clock signal to the time-to-digital conversion device;
the digital loop filter is used for suppressing input noise in the digital phase-locked loop and controlling the output pulse frequency of the oscillator;
the time-to-digital conversion device is used for detecting the time difference between the oscillator clock signal and the reference clock signal.
Compared with the prior art, the embodiment of the invention has the beneficial effects that: according to the embodiment of the invention, the first voltage and the second voltage are output to the first delay circuit and the second delay circuit through the power supply control circuit, so that the first delay circuit and the second delay circuit respectively carry out different delay processing on the first clock signal and the second clock signal only according to different voltages, the measurement precision of the time-to-digital conversion device is determined according to the delay time of the first delay circuit and the second delay circuit, and the time difference between the first constant signal and the second clock signal is obtained according to the time detection circuit. The time-to-digital conversion device reduces the requirements on the process and layout matching of the circuit through controlling the power supply of the delay circuit, and obtains higher time measurement precision.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a time provided by an embodiment of the present invention a system structure schematic diagram of the digital conversion device;
fig. 2 is a circuit diagram of a time-to-digital conversion device according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a power control circuit provided by an embodiment of the present invention;
fig. 4 is a schematic diagram of a digital phase-locked loop device according to an embodiment of the present invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to illustrate the technical scheme of the invention, the following description is made by specific examples.
Example 1
Fig. 1 shows a schematic system configuration of the time-to-digital conversion device, which is described in detail below:
the time-to-digital conversion device provided by the embodiment of the invention comprises: a power supply control circuit 101, a first delay circuit 102, a second delay circuit 103, and a time detection circuit 104.
The power supply control circuit 101 is provided with a first voltage output end and a second voltage output end, the first voltage output end is connected with the first delay circuit 102, and the second voltage output end is connected with the second delay circuit 103; the power control circuit 101 is configured to generate a first voltage and a second voltage, and output the first voltage and the second voltage to the first delay circuit 102 and the second delay circuit 103 through the first voltage output terminal and the second voltage output terminal, respectively.
The first delay circuit 102 receives a first clock signal and is configured to delay the first clock signal according to the first voltage.
And a second delay circuit 103 for receiving a second clock signal and performing delay processing on the second clock signal according to the second voltage.
The time detection circuit 104 is configured to receive the first clock signal and the second clock signal after the delay processing, and detect a time difference between the first clock signal and the second clock signal.
Wherein the first clock signal is delayed by the first delay circuit 102 and the second clock signal is delayed by the second delay circuit 103. The first delay circuit 102 has the same circuit configuration as the second delay circuit 103, so that the specific delay amounts of the first delay unit and the second delay unit are related only to the voltage output from the power supply control circuit 101 to the delay circuits. Meanwhile, the measurement accuracy of the time-to-digital conversion device is related to the delay amounts of the first delay unit and the second delay unit, and the measurement accuracy of the time-to-digital conversion device can be adjusted by adjusting the output voltage of the power supply control circuit.
Alternatively, the first delay circuit 102 includes a plurality of first delay units, and the second delay circuit 103 includes a plurality of second delay units, and the circuit configuration of each first delay unit is the same as that of each second delay unit.
Referring to fig. 2, a circuit diagram of a time-to-digital conversion device is shown. The first delay circuit 102 includes N first delay units, which are sequentially connected in series, and inputs a first clock signal to the first delay circuit 102. For example: the first delay unit is the simplest inverter, and when the input first clock signal is at a logic high value and passes through the first inverter, the inverter inverts the input signal and outputs a logic level opposite to the input signal, i.e. outputs a logic low value, but there is a delay time with a duration of TD1 between the output signal and the input signal. The output logic low value will be delivered as an input signal to the next inverter and a logic high value will be output.
The signal transmission for the second delay circuit is identical to that of the first delay circuit, except that: first, the input clock signals are different; second, the delay time of each delay unit in the second delay circuit is TD2. The difference in delay time between the first delay circuit 102 and the second delay circuit 103 is only related to the voltage input to the delay circuit.
Optionally, the first delay unit is an inverter or a buffer.
It will be readily appreciated that the transmission delay may be different for the basic inverter and buffer when the supply voltages are different. Both the inverter and the buffer are based on CMOS circuits, one characteristic of which is that the transmission delay is related to the supply voltage, the higher the supply voltage input to the delay unit, the smaller the transmission delay of the delay unit; the lower the power supply voltage input to the delay unit, the greater the transmission delay of the delay unit. Based on this characteristic, the inverter and the buffer are used as delay circuits, and different delays are obtained by inputting different voltages to the inverter and the delay.
Optionally, the power supply control circuit 101 includes: a power supply; the voltage dividing circuit is provided with an input end, a first output end and a second output end, wherein the input end is connected with the power supply, and the first output end and the second output end output different voltages; the positive electrode of the first linear voltage stabilizer is connected with the first output end of the voltage dividing circuit, the negative electrode of the first linear voltage stabilizer is connected with the output end, and the output end of the first linear voltage stabilizer is also connected with the first delay circuit; and the positive electrode of the second linear voltage stabilizer is connected with the second output end of the voltage dividing circuit, the negative electrode of the second linear voltage stabilizer is connected with the output end, and the output end of the second linear voltage stabilizer is also connected with the second delay circuit.
With reference to figure 3 of the drawings, a circuit diagram of a power supply control circuit is shown. The power supply control circuit outputs different voltages to the first delay circuit 102 and the second delay circuit 103. The connected power supply is expressed as VREF, a plurality of resistors are arranged from the connected end and the grounding end, and different voltages are obtained by flowing current through different resistors. For example: when the voltage at the first output end of the power supply control circuit is the first reference voltage VREF1, the first linear regulator LDO1 regulates the input first reference voltage VREF1 to obtain a first voltage VDD1, and then outputs the first voltage to the first delay circuit when the positive electrode of the first linear regulator LDO1 is also connected to the first output end. The process of obtaining the second voltage VDD2 by the second linear regulator LDO2 is the same as that of the first linear regulator LDO1, and will not be described here again.
The first linear regulator LDO1 and the second linear regulator LDO2 are preferably low dropout linear regulators, and the circuit structures of the first linear regulator LDO1 and the second linear regulator LDO2 are the same. For the same linear voltage stabilizer, the output first voltage and the output second voltage are different through the difference of the reference voltages of the input voltage stabilizer. The reference voltages input to the first linear regulator LDO1 and the second linear regulator LDO2 may be regulated by registers. The reference voltage can be set into a plurality of gears, and different reference voltages are selected according to the required delay time TD1 of the first delay circuit and the delay time TD2 of the second delay circuit. Specifically, the reference voltages input to the first linear regulator LDO1 and the second linear regulator LDO2 may be set by programming.
Optionally, the time detection circuit 104 includes: a data terminal of an nth trigger is connected to an nth node of the first delay circuit 102, and a clock control terminal of the nth trigger is connected to an nth node of the second delay circuit 103; wherein N is a positive integer.
Referring to fig. 2, the time detection circuit 104 is used herein as a flip-flop, which is an information storage device with a memory function and two stable states, and may be an RS flip-flop, a JK flip-flop, or a D flip-flop, where the selection of a specific flip-flop is not limited. Taking a D trigger as an example, the working principle of the time detection circuit is described. The D flip-flop has a data terminal D, a non-inverting output terminal Q, and a clock control terminal CK, the data terminal of the nth flip-flop is connected to the nth node of the first delay circuit 102, the clock control terminal of the nth flip-flop is connected to the nth node of the second delay circuit 103, the output signal generated by the flip-flop is read out from the output terminal of the flip-flop, and the output signal will be a digital sequence of 0 or 1.
The output sequences Q0 to Qn of the time detection circuit 104 carry time difference information of the first clock signal and the second clock signal. As the first clock signal and the second clock signal propagate in the first delay circuit and the second delay circuit, the time difference between the first clock signal and the second clock signal increases by TD each time the signals pass through one delay unit, where td=td1-TD 2. It is assumed that when the output sequences Q0 to Qm of the time detection circuit are shifted from 1 to 0 or the output sequences Q0 to Qm are shifted from 0 to 1 after passing through the M delay units, it means that the metric time difference between the first clock signal and the second clock signal is m×td. The TD is the time measurement precision of the time-to-digital conversion circuit.
For example, when the first voltage input to the first delay circuit 102 is 1.1V, the delay time corresponding to the first delay unit is 30ps, and when the second voltage input to the second delay circuit 103 is 1.4V, the delay time corresponding to the second delay unit is 20ps, and the time measurement accuracy is 10ps. The time measurement accuracy can be changed by adjusting the magnitudes of the first voltage and the second voltage according to actual needs.
Optionally, the first clock signal is an oscillator clock signal, and the second clock signal is a reference clock signal.
Wherein the frequency of the oscillator clock signal is typically much higher than the frequency of the reference clock signal. After the first clock signal and the second clock signal are input to two delay circuits with different delays, the measurement accuracy of the time-to-digital conversion device can be obtained by calculating the delay time of the two delay circuits, and then the time difference between the oscillation clock signal and the reference clock signal is calculated through a digital sequence output by the time detection circuit.
According to the time-to-digital conversion device, the first voltage and the second voltage are output to the first delay circuit and the second delay circuit through the power supply control circuit, so that the first delay circuit and the second delay circuit respectively carry out different delay processing on the first clock signal and the second clock signal only according to different voltages, the measurement precision of the time-to-digital conversion device is determined according to the delay time of the first delay circuit and the second delay circuit, and the time difference between the first constant signal and the second clock signal is obtained according to the time detection circuit. The time-to-digital conversion device reduces the requirements on the process and layout matching of the circuit through controlling the power supply of the delay circuit, and obtains higher time measurement precision.
Example two
Referring to fig. 4, the present embodiment provides a digital phase locked loop, which includes a digital loop filter 200, a digital voltage controlled oscillator 300, and the time-to-digital conversion apparatus 100 described in the first embodiment; the time-to-digital conversion device 100 is connected to a digital loop filter 200, the digital loop filter 200 is connected to a voltage-controlled oscillator 300, and the voltage-controlled oscillator 300 is also connected to the time-to-digital conversion device 100.
A digital voltage controlled oscillator 300 for outputting an oscillator clock signal to the time to digital conversion device 100.
The output of the vco 300 is a pulse train, and the period of the output pulse train is controlled by the correction signal sent from the digital loop filter 200.
The digital loop filter 200 is used for suppressing input noise in the digital phase-locked loop and also for controlling the output pulse frequency of the digital voltage-controlled oscillator 300.
The digital loop filter 200 filters out the high frequency component output by the time-to-digital conversion device 100, and then applies the output voltage to the input terminal of the digital voltage-controlled oscillator 300, so that the local oscillator signal frequency of the digital voltage-controlled oscillator 300 changes along with the change of the input voltage, and further the output pulse frequency generated by the digital voltage-controlled oscillator 300 is the same as the frequency of the reference clock signal.
The time-to-digital conversion device 100 is configured to detect a time difference between the clock signal of the digital voltage controlled oscillator 300 and a reference clock signal.
The time-to-digital conversion device 100 compares the received oscillator clock signal with the reference clock signal and outputs a time difference or a phase difference therebetween or a voltage proportional to the phase difference. If the oscillator clock signal and the reference clock signal are at exactly the same frequency, the phase difference between them will remain at a constant value, so that the loop is in a "locked state".
Phase locked loops are the core component in solving the synchronization problem, which is in turn a fundamental problem for system performance and applications in modern communication systems. The digital phase-locked loop in this embodiment may be referred to as an all-digital phase-locked loop, because each component of the phase-locked loop in this embodiment is a digitizing circuit.
Compared with the traditional analog phase-locked loop, the digital phase-locked loop has the advantages of high precision, no influence of temperature and voltage, and programmable and adjustable loop bandwidth and center frequency. In addition, the digital phase-locked loop has the characteristics of high reliability, small volume and low price of a digital circuit. A phase locked loop is a phase feedback control system in which the change in the controlled output voltage is discrete rather than continuous, as the error signal is a discrete digital signal rather than an analog signal. To combine the above advantages, digital phase-locked loops have become the direction of the development of phase-locked technology.
The digital phase-locked loop is composed of the time-to-digital conversion device, the digital loop filter and the digital voltage-controlled oscillator in the first embodiment, and the digital voltage-controlled oscillator outputs an oscillator clock signal to the time-to-digital conversion device; suppressing input noise in the digital phase-locked loop by a digital loop filter, and controlling an output pulse frequency to which the digital voltage-controlled oscillator is connected; the time difference between the digital voltage controlled oscillator clock signal and the reference clock signal is detected by a time to digital conversion device. By adopting the time-to-digital conversion device in the first embodiment, the first voltage and the second voltage input to the first delay circuit and the second delay circuit are regulated to obtain different delays, so that the precision of the time-to-digital conversion circuit is improved and has stability, and further, the digital phase-locked loop can obtain higher frequency precision and jitter performance.
It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of the functional units and modules is illustrated, and in practical application, the above-described functional distribution may be performed by different functional units and modules according to needs, i.e. the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-described functions. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, specific names of the functional units and modules are only for convenience of distinguishing from each other, and are not used for limiting the protection scope of the present application. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.
Claims (6)
1. A time-to-digital conversion apparatus, comprising: a power supply control circuit, a first delay circuit, a second delay circuit, and a time detection circuit;
the power supply control circuit is provided with a first voltage output end and a second voltage output end, the first voltage output end is connected with the first delay circuit, and the second voltage output end is connected with the second delay circuit; the power supply control circuit is used for generating a first voltage and a second voltage, and outputting the first voltage and the second voltage to the first delay circuit and the second delay circuit respectively through the first voltage output end and the second voltage output end;
a first delay circuit for receiving a first clock signal and performing delay processing on the first clock signal according to the first voltage;
the second delay circuit is used for receiving a second clock signal and carrying out delay processing on the second clock signal according to the second voltage;
a time detection circuit for receiving the first clock signal and the second clock signal after the delay processing and detecting a time difference between the first clock signal and the second clock signal;
the first delay circuit comprises a plurality of first delay units, the second delay circuit comprises a plurality of second delay units, and the circuit structure of the first delay units is the same as that of the second delay units;
the specific delay amounts of the first delay unit and the second delay unit are only related to the voltage output by the power supply control circuit to the delay circuit;
the difference in delay time between the first delay circuit and the second delay circuit is dependent only on the voltage input to the delay circuit.
2. The time-to-digital conversion apparatus according to claim 1, wherein the first delay unit is an inverter or a buffer.
3. The time-to-digital conversion apparatus according to claim 1, wherein the power supply control circuit includes:
a power supply;
the voltage dividing circuit is provided with an input end, a first output end and a second output end, wherein the input end is connected with the power supply, and the first output end and the second output end output different voltages;
the positive electrode of the first linear voltage stabilizer is connected with the first output end of the voltage dividing circuit, the negative electrode of the first linear voltage stabilizer is connected with the output end, and the output end of the first linear voltage stabilizer is also connected with the first delay circuit;
and the positive electrode of the second linear voltage stabilizer is connected with the second output end of the voltage dividing circuit, the negative electrode of the second linear voltage stabilizer is connected with the output end, and the output end of the second linear voltage stabilizer is also connected with the second delay circuit.
4. The time-to-digital conversion apparatus according to claim 1, wherein the time detection circuit includes:
the data end of the Nth trigger is connected with the Nth node of the first delay circuit, and the clock control end of the Nth trigger is connected with the Nth node of the second delay circuit; wherein N is a positive integer.
5. A time to digital conversion apparatus according to any one of claims 1 to 4, wherein the first clock signal is an oscillator clock signal and the second clock signal is a reference clock signal.
6. A digital phase locked loop comprising a digital loop filter, a digital voltage controlled oscillator and a time to digital conversion device according to any one of claims 1 to 5; the time-to-digital conversion device is connected with the digital loop filter, the digital loop filter is connected with the digital voltage-controlled oscillator, and the digital voltage-controlled oscillator is also connected with the time-to-digital conversion device;
the digital voltage-controlled oscillator is used for outputting an oscillator clock signal to the time-to-digital conversion device;
the digital loop filter is used for suppressing input noise in a digital phase-locked loop and controlling the output pulse frequency of the digital voltage-controlled oscillator;
the time-to-digital conversion device is used for detecting the time difference between the digital voltage-controlled oscillator clock signal and the reference clock signal.
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| IT201900008793A1 (en) * | 2019-06-13 | 2020-12-13 | Fond Bruno Kessler | POWER CIRCUIT MODULE FOR TDC AND CALIBRATION METHOD OF SAID POWER CIRCUIT MODULE |
| CN110673113B (en) * | 2019-08-16 | 2021-08-10 | 西安电子科技大学 | High-precision low-kickback-noise clock regeneration delay chain |
| CN112824983B (en) * | 2019-11-20 | 2022-08-19 | 圣邦微电子（北京）股份有限公司 | Time measuring circuit, time measuring chip and time measuring device |
| CN111061145B (en) * | 2019-12-30 | 2022-07-05 | 嘉兴泰传光电有限公司 | Time delay settable time interval measuring device and measuring method based on FPGA |
| WO2022110235A1 (en) * | 2020-11-30 | 2022-06-02 | 华为技术有限公司 | Chip and clock detection method |
| CN114199519B (en) * | 2021-10-31 | 2024-04-16 | 昆山丘钛光电科技有限公司 | Testing device and system |
| CN114995092B (en) * | 2022-06-15 | 2024-02-23 | 西安电子科技大学芜湖研究院 | Time-to-digital conversion circuit |
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| CN101694998A (en) * | 2009-10-23 | 2010-04-14 | 中兴通讯股份有限公司 | Locking system and method |
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