CN103856281A - Data synchronization method - Google Patents
Data synchronization method Download PDFInfo
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- CN103856281A CN103856281A CN201210509967.3A CN201210509967A CN103856281A CN 103856281 A CN103856281 A CN 103856281A CN 201210509967 A CN201210509967 A CN 201210509967A CN 103856281 A CN103856281 A CN 103856281A
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- synchronizing signal
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Abstract
The embodiment of the invention provides a data synchronization method and device. The method includes the first step of carrying out one-to-N demultiplexing on input data through set asynchronous clocks to obtain N paths of data and first synchronizing signals, wherein the transmission rate of each path of data is one-Nth of the transmission rate of the input data, and the cycle of the first synchronizing signals is the cycle of 2N asynchronous clocks, the second step of carrying out delaying on the first synchronizing signals through set synchronous clocks to obtain second synchronizing signals and third synchronizing signals, the third step of judging whether the second synchronizing signals are equal to the third synchronizing signals at each sampling edge of the synchronous clocks, generating edge trigger signals and carrying out counting operation, and the fourth step of carrying out sampling on the N paths of data sequentially according to the synchronous clocks and output counting values to obtain N-to-one multiplex output data. The method solves the problems that requirements for RAM resources are high and the delay time is long.
Description
Technical field
The present invention relates to digital signal transmission field, relate in particular to a kind of synchronous method of data and device.
Background technology
Along with the scale of digital system is increasing, complexity is more and more higher, the application of two or more clock zones in logical design is more and more.In different clock zones, inevitably can run into the mutual transmission of data.Owing to can having certain phase difference and frequency jitter in short-term between two different clocks, in order to make the data can transmitting, in the time designing, the impact of ordered pair function must take into full account time, otherwise can shine into two failure of data synchronization between clock zone.
At present, data are transformed into synchronous clock domains by asynchronous clock domain adopts the method for double-interface RAM buffer data to realize conventionally: the clock of writing with asynchronous clock as dual port RAM, write the write address of clock generating dual port RAM, by writing clock at a port data writing; Again with synchronised clock as reading clock, and the address of reading that produces dual port RAM, reads clock in another port sense data; This dual port RAM degree of depth is that the scope of frequency difference in short-term of tolerating is as required determined.Respectively read/write address sampled with synchronised clock and compare, to judge whether the distance between read/write address is less than the minimum range that reading and writing conflict may occur, i.e. " risk distance ", if, will read address redirect, and forward to behind current location address farthest, then carry out read operation; Read address otherwise needn't adjust, directly carry out read operation.
The data that read out through said method, although can reach not only stable but also correct, can also shield phase difference between asynchronous clock and local synchronous clock and frequency jitter problem in short-term, the data that can realize asynchronous clock domain are synchronous, but the method for utilization, need to rely on the RAM resource of programmable logic device, in addition, the delay time of synchrodata is longer, need to be determined by the projected depth of dual port RAM.
Summary of the invention
The embodiment of the present invention provides a kind of synchronous method of data and device, in order to solve problem higher to the depth requirements of RAM in available data simultaneous techniques and that delay time is grown.
Based on the problems referred to above, a kind of synchronous method of data that the embodiment of the present invention provides, comprising:
Utilize the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, the N circuit-switched data and the cycle that obtain every road transmission rate and be the 1/N of the data of input are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, described the second synchronizing signal and described the 3rd synchronizing signal differ at least one synchronised clock cycle;
On each sampling edge of described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and judging for the first time when unequal, generate along triggering signal and be counted as the first numerical value of setting, and proceed counting according to the cycle of synchronised clock being counted as after the first numerical value of setting, on once judging along the moment of triggering signal on generating, whether the numerical value of a counting is the second value of setting, and if so, proceeds counting; If not, be counted as the first numerical value of described setting; The numerical value of the each counting of output successively;
Utilize the numerical value of each counting of described synchronised clock and output, successively described N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
The synchronous device of a kind of data that the embodiment of the present invention provides, comprising:
Demultiplexing module, for the asynchronous clock that utilizes setting, the data of input are carried out to 1:N demultiplexing, the N circuit-switched data and the cycle that obtain every road transmission rate and be the 1/N of the data of input are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Synchronization module, for utilizing the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal obtaining through described demultiplexing module, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle, with the each sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and generate along triggering signal when unequal;
Counting module, being used for receiving described synchronization module generates along triggering signal judging for the first time when unequal, and be counted as the first numerical value of setting, and proceed counting according to the cycle of synchronised clock being counted as after the first numerical value of setting, described counting module receive that described synchronization module generates upper once judge along the moment of triggering signal on the numerical value of a counting whether be the second value of setting, if so, proceed counting; If not, be counted as the first numerical value of described setting; Described counting module is exported the numerical value of each counting successively;
Multiplexing module, for utilizing the numerical value of each counting of described synchronised clock and described counting module output, samples to described N circuit-switched data successively, obtains the multiplexing output data of N:1.
The beneficial effect of the embodiment of the present invention comprises: synchronous method and the device of data that the embodiment of the present invention provides, utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input obtains after N circuit-switched data and the first synchronizing signal, the synchronised clock that recycling is set postpones to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, then judge according to synchronised clock sampling edge whether the second synchronizing signal and the 3rd synchronizing signal equate, generate and carry out counting operation along triggering signal, finally utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled and can be obtained synchrodata.The embodiment of the present invention can make the data of input generate after multichannel data at demultiplexing, according to two-way synchronizing signal is compared, flip-flop number is counted, according to the numerical value of counter, multichannel data is sampled and multiplexing output, reduce the time delay of transfer of data, avoid in available data simultaneous techniques, the RAM resource that need to rely on programmable logic device solves the synchronous problem of data, simultaneously, the synchronizing relay of data also can be controlled preferably, need to not decided by the projected depth of dual port RAM.
Brief description of the drawings
The flow chart of the synchronous method of data that Fig. 1 provides for the embodiment of the present invention;
One of sequential chart of the data synchronization process that Fig. 2 provides for the embodiment of the present invention;
Two of the sequential chart of the data synchronization process that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the synchronous device of data that Fig. 4 provides for the embodiment of the present invention;
Synchronization module and the mutual schematic diagram of counting module that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description, the method that a kind of data that the embodiment of the present invention is provided are synchronous and the embodiment of device describe.
A kind of synchronous method of data that the embodiment of the present invention provides, as shown in Figure 1, specifically comprises the following steps:
S101: utilize the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, the N circuit-switched data and the cycle that obtain every road transmission rate and be the 1/N of the data of input are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is greater than 1 integer.
Preferably, above-mentioned the first synchronizing signal can obtain by following manner:
As rising edge or the trailing edge of the first synchronizing signal, to be at least greater than the pulse duration of 2 asynchronous clock cycles as the first synchronizing signal, obtain the first synchronizing signal using the frame head position of any circuit-switched data after demultiplexing.
Particularly, in embodiments of the present invention, can adopt rising edge or the trailing edge of the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, in the process of demultiplexing, make the speed of the data of input drop to original 1/N.
As shown in Figure 2, taking homology but have transmission delay change asynchronous clock as example, suppose N=3, utilize the rising edge of asynchronous clock to carry out demultiplexing to 1 circuit-switched data (data A+ data B+ data C) of input, after demultiplexing, export respectively 3 circuit-switched data in t1 moment, t2 moment and t3 moment, i.e. data D
0(the data A after corresponding speed reduces), data D
1(the data B after corresponding speed reduces) and data D
2(the data C after corresponding speed reduces); With the data D in t1 moment
0for example, output data D
0time speed be in 1 circuit-switched data of original input data A 1/3;
In this process, also with data D
0frame head position as rising edge, to be at least greater than first synchronizing signal (sync) in cycle as 6 asynchronous clock cycles that 2 asynchronous clock cycles obtain as pulse duration.In embodiments of the present invention, for ensure the synchronised clock of follow-up setting can reliable samples to data, the pulse duration of sync need at least be greater than 2 asynchronous clock cycles.
S102: utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, the second synchronizing signal and the 3rd synchronizing signal differ a synchronised clock cycle.
Preferably, the second synchronizing signal and the 3rd synchronizing signal obtain by following manner:
According to the rising edge of synchronised clock or trailing edge, the first synchronizing signal is postponed, obtain the second synchronizing signal;
A synchronised clock cycle of the second sync signal delay is obtained to the 3rd synchronizing signal.
As shown in Figure 2, adopt the trailing edge of synchronised clock to postpone the sync obtaining, obtain the second synchronizing signal (sync1) in the k0 moment, sync1 is postponed to 1 synchronizing cycle and obtain the 3rd synchronizing signal (sync2) in the k1 moment.
S103: on each sampling edge of synchronised clock, judge whether the second synchronizing signal and the 3rd synchronizing signal equate, and judging for the first time when unequal, generate along triggering signal and be counted as the first numerical value of setting, and proceed counting according to the cycle of synchronised clock being counted as after the first numerical value of setting, on once judging along the moment of triggering signal on generating, whether the numerical value of a counting is the second value of setting, and if so, proceeds counting; If not, be counted as first of setting and set numerical value; The numerical value of the each counting of output successively.
Preferably, the above-mentioned M digit counter that can utilize is counted, wherein M=
┏log
2n
┐, the value of M is log
2on N, round.
In above-mentioned steps S103, the each sampling that adopts synchronised clock is along judging for the first time sync1 and sync2 when unequal, and generation is along triggering signal, in this moment, counter starts counting, is counted as the first numerical value of setting, and the first numerical value refers to that counter starts the numerical value of counting.In embodiments of the present invention, counter can carry out accumulated counts from 0 to N-1, also can carry out countdown from N-1 to 0, can also count since 2 or 3 etc., and the first numerical value of setting can be 0,2,3 or N-1 etc.
Particularly, in the time of practical application, can cause for fear of loss of clock or burr the slip of exporting data, in the upper moment once generating along triggering signal, can judge last count value, be the second value of setting if judge last count value, counter need not be adjusted, continue to count according to the count cycle (the synchronised clock same period) cumulative (or successively decreasing), if not the second value of setting, rolling counters forward is the first numerical value of setting.In this bright embodiment, the second value of setting be for follow-up generation along moment of triggering signal on numerical value that once count value of counter judges, the value of second value can be selected flexibly, for example, the second value of setting can be 2, can be also 5,6 or 0.In embodiments of the present invention, the first numerical value of setting and the second value of setting can be identical, also can be different.
As shown in Figure 2, suppose N=3, M=2, adopt 2 digit counters to count, in Fig. 2, suppose that the first numerical value of setting is 0, be that counter is since 0 counting, the second value of setting is 2, and in the y0 moment producing along triggering signal, judging last count results is 2, be the second value of setting, this hour counter is proceeded counting, is counted as 0, follow-uply exports respectively 1,2 and 0 at y1, y2 and y3 moment.
S104: utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
Preferably, the embodiment of the present invention can utilize synchronised clock from arbitrary count value, successively N circuit-switched data is sampled, and obtains the multiplexing output data of N:1.
As shown in Figure 2, be output as 0 at y0 time trigger counter, synchronised clock is sampled as 0 in the y1 moment to counter, according to count value 0 to data D
0sampling output (one piece of data A)
;in the y2 moment, according to count value 1 to data D
1sampling output (one piece of data B); In the y3 moment according to count value 2 to data D
2sampling output (one piece of data C).Concrete sampling process belongs to prior art, does not repeat them here.
Above-mentioned Fig. 2 is the explanation of the embodiment of the present invention being carried out as an example of N=3 example, for comprising D (0), D (1) ... D (N-1) multiple segment data utilizes asynchronous clock the data of input to be carried out to the situation of 1:N demultiplexing, as shown in Figure 3, asynchronous clock adopts rising edge processing, in the t0 moment, input data are started to demultiplexing, after demultiplexing, in the time of ensuing t1, be carved into respectively N the clock cycle in t (N) moment, export respectively D
0,
?d
1,
?d
2.... D
n-1the altogether data after the demultiplexing of N road, the speed of every circuit-switched data is originally to input the 1/N of data, synchronizing signal sync is taking 2N asynchronous clock width as the cycle, in t0 moment saltus step, and D
0frame head aligned in position.By sync and synchronised clock, obtain postpone after synchronizing signal sync1 and sync2, by both relatively after, rolling counters forward is 0,1,2 ... N-1, according to the value of rolling counters forward respectively to D
0,
?d
1,
?d
2.... D
n-1sample, multiplexing output data.D (0)
,, D (1)
,data and D
0,
?d
1,
?d
2.... D
n-1the synchronous method of data is similar.
Based on same inventive concept, the embodiment of the present invention also provides a kind of data synchronous device, the method that the principle of dealing with problems due to this device is synchronizeed with aforementioned data is similar, and therefore the enforcement of this device can be referring to the enforcement of preceding method, repeats part and repeat no more.
As shown in Figure 4, the embodiment of the present invention provides data synchronous device, comprising:
Preferably, demultiplexing module 401 is rising edge or the trailing edge as the first synchronizing signal specifically for the frame head position of any circuit-switched data after demultiplexing, to be at least greater than the pulse duration of 2 asynchronous clock cycles as the first synchronizing signal, obtain the first synchronizing signal.
Preferably, synchronization module 402, specifically for according to the rising edge of synchronised clock or trailing edge, the first synchronizing signal being postponed, obtains the second synchronizing signal; A synchronised clock cycle of the second sync signal delay is obtained to the 3rd synchronizing signal.
Preferably, counting module 403 is
┏log
2n
┐counter.
In embodiments of the present invention, synchronization module 402 in the specific implementation, can the signal synchronization unit 501(by as shown in Figure 5 generate two-way synchronizing signal sync1 and sync2), judging unit 502(judges whether to equate to two-way synchronizing signal) and M digit counter 403 realize, certainly, the embodiment of the present invention is also not limited to this kind of concrete structure zoned format.
Preferably, Multiplexing module 404 can utilize synchronised clock from arbitrary count value, successively N circuit-switched data is sampled, and obtains the multiplexing output data of N:1.
Synchronous method and the device of data that the embodiment of the present invention provides, utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input obtains after N circuit-switched data and the first synchronizing signal, the synchronised clock that recycling is set postpones to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, then judge according to synchronised clock sampling edge whether the second synchronizing signal and the 3rd synchronizing signal equate, generate and carry out counting operation along triggering signal, finally utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled and can be obtained synchrodata.The embodiment of the present invention can make the data of input generate after multichannel data at demultiplexing, according to the count value that two-way synchronizing signal is compared to generation, to multichannel data sampling synchronous output, reduce the time delay of transfer of data, avoided in available data simultaneous techniques, the RAM resource that need to rely on programmable logic device solves the synchronous problem of data, simultaneously, the synchronizing relay of data also can be controlled preferably, need to not decided by the projected depth of dual port RAM.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if these amendments of the present invention and within modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (8)
1. the synchronous method of data, is characterized in that, comprising:
Utilize the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, the N circuit-switched data and the cycle that obtain every road transmission rate and be the 1/N of the data of input are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle;
On each sampling edge of described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and judging for the first time when unequal, generate along triggering signal and be counted as the first numerical value of setting, and proceed counting according to the cycle of synchronised clock being counted as after the first numerical value of setting, on once judging along the moment of triggering signal on generating, whether the numerical value of a counting is the second value of setting, if, proceed counting, if not, be counted as the first numerical value of described setting; The numerical value of the each counting of output successively;
Utilize the numerical value of each counting of described synchronised clock and output, successively described N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
2. the method for claim 1, is characterized in that, the first synchronizing signal obtains by following manner:
As rising edge or the trailing edge of the first synchronizing signal, to be at least greater than the pulse duration of 2 asynchronous clock cycles as the first synchronizing signal, obtain described the first synchronizing signal using the frame head position of any circuit-switched data after demultiplexing.
3. the method for claim 1, is characterized in that, utilizes the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, comprising:
According to the rising edge of described synchronised clock or trailing edge, described the first synchronizing signal is postponed, obtain described the second synchronizing signal;
A synchronised clock cycle of described the second sync signal delay is obtained to described the 3rd synchronizing signal.
4. the method for claim 1, is characterized in that, utilizes M digit counter to count, wherein M=
┏log
2n
┐.
5. the synchronous device of data, is characterized in that, comprising:
Demultiplexing module, for the asynchronous clock that utilizes setting, the data of input are carried out to 1:N demultiplexing, the N circuit-switched data and the cycle that obtain every road transmission rate and be the 1/N of the data of input are first synchronizing signal in 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Synchronization module, for utilizing the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal obtaining through described demultiplexing module, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle, with the each sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and generate along triggering signal when unequal;
Counting module, being used for receiving described synchronization module generates along triggering signal judging for the first time when unequal, and be counted as the first numerical value of setting, and proceed counting according to the cycle of synchronised clock being counted as after the first numerical value of setting, described counting module receive that described synchronization module generates upper once judge along the moment of triggering signal on the numerical value of a counting whether be the second value of setting, if so, proceed counting; If not, be counted as the first numerical value of described setting; Described counting module is exported the numerical value of each counting successively;
Multiplexing module, for utilizing the numerical value of each counting of described synchronised clock and described counting module output, samples to described N circuit-switched data successively, obtains the multiplexing output data of N:1.
6. the synchronous device of data as claimed in claim 5, it is characterized in that, described Multiplexing module, rising edge or trailing edge specifically for the frame head position of any circuit-switched data after demultiplexing as the first synchronizing signal, to be at least greater than the pulse duration of 2 asynchronous clock cycles as the first synchronizing signal, obtain described the first synchronizing signal.
7. the synchronous device of data as claimed in claim 5, is characterized in that, described synchronization module, specifically for according to the rising edge of described synchronised clock or trailing edge, described the first synchronizing signal being postponed, obtains described the second synchronizing signal; A synchronised clock cycle of described the second sync signal delay is obtained to described the 3rd synchronizing signal.
8. the synchronous device of data as claimed in claim 5, is characterized in that, described counting module is that figure place is
┏log
2n
┐counter.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104730483A (en) * | 2015-03-13 | 2015-06-24 | 郑州万特电气股份有限公司 | Wireless pulse synchronous sampling method |
| CN110504968A (en) * | 2018-05-17 | 2019-11-26 | 四川锦江电子科技有限公司 | A kind of double asynchronous signal sample count apparatus and method |
-
2012
- 2012-12-04 CN CN201210509967.3A patent/CN103856281A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104730483A (en) * | 2015-03-13 | 2015-06-24 | 郑州万特电气股份有限公司 | Wireless pulse synchronous sampling method |
| CN104730483B (en) * | 2015-03-13 | 2017-07-28 | 郑州万特电气股份有限公司 | A kind of wireless pulses synchronous sampling method |
| CN110504968A (en) * | 2018-05-17 | 2019-11-26 | 四川锦江电子科技有限公司 | A kind of double asynchronous signal sample count apparatus and method |
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Application publication date: 20140611 |