CN102833024B - Method and the equipment of generation time stamp - Google Patents
Method and the equipment of generation time stamp Download PDFInfo
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- CN102833024B CN102833024B CN201110159174.9A CN201110159174A CN102833024B CN 102833024 B CN102833024 B CN 102833024B CN 201110159174 A CN201110159174 A CN 201110159174A CN 102833024 B CN102833024 B CN 102833024B
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Abstract
Stab in order to solve current cross clock domain passing time the technical problem that delay is large, hardware cost is high of bringing, the invention provides method and the equipment of generation time stamp, this equipment comprises the first circuit, for receiving the first clock; The second circuit, for receiving second clock; Detecting unit, for detecting each rising edge of described the first clock based on described second clock; Timestamp generation unit, in the time that described detecting unit detects described rising edge, control time stamp increases the time span corresponding to the cycle of described the first clock. In the present invention, timestamp directly upgrades according to the rising edge of the first clock detecting based on second clock, timestamp can be reflected more exactly and the variation of the first clock reduced mistake; And, avoid the larger timestamp of the data volume of the first clock generating to transmit and process, reduce from request time and stabbed the delay obtaining between timestamp, also reduce system complex degree and hardware cost.
Description
Technical field
The present invention relates to the simultaneous techniques in communication, relate in particular to the generation technology of timestamp.
Background technology
In IEEE1588v2 system, the clock that use is recovered by IEEE1588 algorithm is at present as the driving of local time stamp counter. In the time that the bag of PHY side arrives, IEEE1588 processor can use this local time stamp counter, this bag is stamped to the timestamp of due in.
In current IEEE1588 system, IEEE1588 recover for driving the clock frequency of local time stamp counter lower, be for example 25MHz. Therefore, local time stamp counter works is at the clock zone of 25MHz. But in system, phy interface and IEEE1588 processor are the clock zones that is operated in 125MHz. Therefore,, when system detects the bag of arrival and need to obtain and timestamp is beaten in the time that this is wrapped, this system must be delivered to 125MHz system clock territory from the IEEE1588 clock zone of 25MHz by the timestamp of the clock generating by 25MHz. In general, the length of timestamp is 80 bits. The principle of this technical scheme as shown in Figure 1.
For this timestamp is delivered to 125MHz system clock territory from IEEE1588 clock zone, there are in the industry at present two kinds of solutions: sampling voting method and asynchronous FIFO (FIFO) method.
In sampling voting method, local time stamp maker is in 25MHz clock zone, and in its 80 registers that each bit of the timestamp of generation is deposited with respectively, each register has been deposited the logical value of the each bit in 80 bits of timestamp one by one. Those registers are connected on 80 registers that are positioned at 125MHz clock zone one by one by logic respectively. The clock of 125MHz drives and reads these 80 registers of 125MHz clock zone, thereby obtains timestamp in 125MHz clock zone. Because the line length of register between two territories differs, may there is difference in the time of the acquisition of the register in 125MHz clock zone actual value therefore. Therefore, in sampling voting method, when IEEE1588 processor receives after timestamp request, use the clock of 125MHz, each register to 125MHz clock zone carries out repeatedly, for example three samplings, and respectively for each in 80 registers, using at least two equal sampled values as timestamp the actual value at this bit, thereby obtain the timestamp of 80 bits. Fig. 1 shows the sequential chart of sampling voting method. Visible, owing to having carried out repeatedly sampling, the time that obtains final voting result will be later than the time of timestamp request greatly. In general, as shown in Figure 2, IEEE1588 processor is request time stamp in the time 11 and 18, and voting result just produces respectively and offer IEEE1588 processor in the time 12 and 19, has produced certain delay. Under some extreme cases, for example, for the timestamp request in the time 13 in Fig. 2, it arrives at times 13 end of 25MHz clock, because next clock cycle of 25MHz clock arrives immediately, the register of 125MHz clock zone may be updated to the timestamp corresponding to next clock cycle of 25MHz clock, due to repeatedly voting, may adjudicate the timestamp of next clock cycle 14 correspondence that obtains 25MHz clock at 125MHz clock zone, this has just caused wrong generation. And sampling voting method also needs to take more resource. To adopt ALTERAEP2AGX125EF29I5 to realize sampling voting method as example, as shown in Figure 3, need to use 91 LUT (logical block table) and 325 special registers that use as function generator.
In asynchronous FIFO (FIFO) method, local time stamp maker is in 25MHz clock zone, and its each bit by the timestamp of generation stores into respectively in a buffer (Buffer), and storing frequencies should be 25MHz. The output of this buffer is positioned at 125MHz clock zone, is subject to the driving of 125MHz clock from this buffer, to read the timestamp that enters at first buffer. But can there is certain delay in asynchronism first in first out method. As shown in Figure 4, IEEE1588 processor request time stamp in the time 11,13 and 18. Within the identical time 11,13 and 18, produce respectively response. But the timestamp that obtains was respectively the timestamp of a upper time 10,12 and 17. The timestamp that is this moment cannot be passed in the clock zone of 125MHz in time. And asynchronism first in first out method also needs to take more resource. To adopt ALTERAEP2AGX125EF29I5 to realize asynchronous first-in first-out method as example, as shown in Figure 5, in the situation that using M9K block RAM, need to use 79 LUT (logical block table), 89 special registers and 4 M9K pieces that use as function generator. As shown in Figure 6, in the situation that using MLABRAM, need to use 215 LUT (logical block table) and 669 special registers that each and every one use as function generator.
Visible, all there is certain delay in the technology of the existing timestamp producing at 125MHz clock zone acquisition 25MHz clock zone, and these technology all need to take more resource.
Summary of the invention
Therefore, need to provide a kind of technology that postpones little acquisition timestamp. Preferably, this technology also should take less resource, has lower design complexities.
According to an aspect of the present invention, provide a kind of method of generation time stamp, it is characterized in that, comprised the steps:
-reception the first clock;
-detect each rising edge of described the first clock based on second clock;
-in the time described rising edge being detected, control time stamp increases the time span corresponding to the cycle of described the first clock
In this aspect, timestamp directly upgrades according to the rising edge of the first clock detecting based on second clock, timestamp can be reflected more exactly and the variation of the first clock reduced mistake; And this aspect has avoided the larger timestamp of the data volume of the first clock generating to transmit and process, and has reduced from request time and has stabbed the delay obtaining between timestamp, has also reduced system complex degree.
Preferred embodiment the method is the method at second clock territory generation time stamp according to one, and described receiving step receives described the first clock from the first clock zone in described second clock territory.
This preferred embodiment provides the method that produces the timestamp based on the first clock in second clock territory, is specially adapted to the application scenario of cross clock domain acquisition time stamp.
According to another preferred embodiment, described the first clock is the IEEE1588 clock being resumed; Described second clock is the system works clock of IEEE1588 processor or physical interface.
This is preferred embodiment applied in IEEE1588 system, has solved this system and need to obtain in system clock territory the technical problem corresponding to the timestamp of IEEE1588 clock.
According to another aspect of the present invention, provide a kind of equipment of generation time stamp, it is characterized in that, having comprised:
The-the first circuit, for receiving the first clock;
The-the second circuit, for receiving second clock;
-detecting unit, for detecting each rising edge of described the first clock based on described second clock;
-timestamp generation unit, in the time that described detecting unit detects described rising edge, control time stamp increases the time span corresponding to the cycle of described the first clock.
In this aspect, make timestamp can reflect more exactly the variation of the first clock; And this aspect has avoided the larger timestamp of the data volume of the first clock generating to process, and has reduced from request time and has stabbed the delay obtaining between timestamp. And this equipment does not need to take buffer, experimental results show that logical block table and register that this aspect takies are also less.
According to one preferred embodiment, described the first circuit is single-bit circuit.
The first clock that this preferred embodiment only needs to transmit single-bit, does not need to transmit for example timestamp of 80 bits, greatly reduces the complexity of equipment.
Other advantage of the present invention, aspect and characteristic will be described below, or explanation by below and being understood by those skilled in the art
Brief description of the drawings
Only by example, the preferred embodiments of the present invention are more specifically described with reference to the following drawings hereinafter:
Fig. 1 shows the schematic diagram of existing cross clock domain passing time stamp;
Fig. 2 shows existing sampling voting method, existing asynchronous first-in first-out method and sequential chart separately according to the embodiment of the present invention;
Fig. 3 shows the shared resource of existing sampling voting method;
Fig. 4 shows and uses M9K to realize the shared resource of existing asynchronous first-in first-out method;
Fig. 5 shows and uses MLAB to realize the shared resource of existing asynchronous first-in first-out method;
Fig. 6 shows according to the schematic diagram of generation time stamp of the present invention;
Fig. 7 shows according to the shared resource of equipment of generation time stamp of the present invention.
In accompanying drawing, same or analogous Reference numeral represents same or analogous steps characteristic or parts (module) feature.
Detailed description of the invention
Below with reference to Fig. 6 to Fig. 7, method and apparatus according to the invention is described in detail.
Fig. 6 shows according to the schematic diagram of generation time stamp of the present invention, and equipment according to the present invention comprises:
The-the first circuit, for receiving the first clock, for example 25MHzIEEE1588 clock in Fig. 6;
The-the second circuit, for receiving second clock, for example 125MHz system clock in Fig. 6;
-detecting unit, for detecting each rising edge of the first clock based on second clock; And
-timestamp generation unit, in the time that described detecting unit detects the rising edge of the first clock, control time stamp increases the time span corresponding to the cycle of the first clock.
According to the method for generation time stamp of the present invention, comprise the steps:
-reception the first clock;
-detect each rising edge of described the first clock based on second clock;
-in the time described rising edge being detected, control time stamp increases the time span corresponding to the cycle of described the first clock
In general, 25MHzIEEE1588 clock itself is single-bit, as shown in Figure 6. Therefore, the first circuit is also single-bit, just can complete the function of 25MHzIEEE1588 clock being introduced to the detecting unit in 125MHz system clock territory, and needn't as prior art, use the data/address bus of 80 bits that the 80 bit timestamps that produce in 25MHzIEEE1588 clock zone are introduced to 125MHz system clock territory. Present embodiment has been simplified design, and has also reduced shared logical resource.
Be introduced into after detecting unit at 25MHzIEEE1588 clock, detecting unit, based on 125MHz system clock, detects each rising edge of the first clock. Concrete, detecting unit can be within each cycle of 125MHz system clock, and for example rising edge triggers, and detects the logical value of 25MHzIEEE1588 clock, i.e. level. If testing result is low level within a certain cycle of 125MHz system clock, and testing result is high level within next cycle immediately, so just mean that 25MHzIEEE1588 clock exists a rising edge.
Detecting after rising edge, detecting unit can pass through a triggering signal, and a for example pulse, by 25MHzIEEE1588 clock generation rising edge notifying time stamp generation unit.
When timestamp generation unit receives this triggering signal, control time stamp increases the time span corresponding to the cycle of 25MHzIEEE1588 clock, for example, increase by 40 nanoseconds, and the timestamp after increase is as up-to-date timestamp. This up-to-date timestamp can be deposited in the register of 80 bits. Deposited a upper timestamp if this register is realized, so up-to-date timestamp covers information before.
For example, after first rising edge of the IEEE1588 clock in Fig. 6 arrives, detecting unit detects this rising edge. Because digital circuit is the relation that driven by 125MHz system clock, timestamp generation unit will generate the timestamp increasing progressively, i.e. time 11 in the time that next 125MHz system clock arrives. With respect to delay of the prior art, as shown in Figure 6, delay of the present invention has obtained controlling significantly. And, by improving the frequency of clock, this delay can be reduced further.
Any moment within the time 11, for example corresponding moment of timestamp request in Fig. 6, IEEE1588 processor request time stamp, timestamp generation unit can offer IEEE1588 processor by up-to-date timestamp immediately. For example, IEEE1588 processor directly reads 80 bit register and can obtain up-to-date timestamp. Therefore, present embodiment can in time, for example, offer timestamp IEEE1588 processor immediately, has reduced delay.
Afterwards, to each rising edge of IEEE1588 clock, above operation repeats. As shown in Figure 6, timestamp be updated to successively 12,13,14....... In the time 13 and 18, IEEE1588 processor request and obtain immediately corresponding timestamp.
Consider the shared resource of the present invention, to adopt ALTERAEP2AGX125EF29I5 to realize sampling voting method as example, as shown in Figure 7, only need to use 65 LUT (logical block table) and 66 special registers that use as function generator. Visible, with respect to prior art, the shared resource of the present invention is less.
Although illustrate in detail and described the present invention in accompanying drawing and aforesaid description, should think that this is illustrated and describes is illustrative and exemplary, instead of restrictive; The invention is not restricted to above-mentioned embodiment.
The those skilled in the art of those the art can, by research description, disclosed content and accompanying drawing and appending claims, understand and implement other changes of the embodiment to disclosing. In practical application of the present invention, a part may execute claims the function of middle quoted multiple technical characterictics. In the claims, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number. Any Reference numeral in claim should not be construed as the restriction to scope.
Claims (11)
1. a method for generation time stamp in second clock territory, is characterized in that, comprisesFollowing steps:
-in described second clock territory, receive from the first clock of the first clock zone;
-second clock based on described second clock territory detects on each of described the first clockRise edge;
-in the time described rising edge being detected, control time stamp increases corresponding to described first o'clockThe time span in the cycle of clock, and using the timestamp after this increase as up-to-date timestamp.
2. method according to claim 1, is characterized in that, described the first clock byThe IEEE1588 clock recovering;
Described second clock is the system works clock of IEEE1588 processor or physical interface.
3. method according to claim 2, is characterized in that, of described second clockOne frequency is three times or above multiple of the first frequency of described the first clock.
4. method according to claim 3, is characterized in that, described first frequency is25MHz, described second frequency is 125MHz.
5. method according to claim 1, is characterized in that, also comprises the steps:
-reception carrys out the timestamp request of self processor;
-provide up-to-date described timestamp to described processor.
6. an equipment for generation time stamp in second clock territory, is characterized in that, comprising:
The-the first circuit, for receiving from the of the first clock zone in described second clock territoryOne clock;
The-the second circuit, for receiving the second clock in described second clock territory;
-detecting unit, for detecting each of described the first clock based on described second clockRise edge;
-timestamp generation unit, for whenever described detecting unit detects described rising edgeTime, control time stamp increases the time span corresponding to the cycle of described the first clock, and thisTimestamp after increase is as up-to-date timestamp.
7. equipment according to claim 6, is characterized in that, described the first circuit is singleBit line.
8. equipment according to claim 6, is characterized in that, described the first clock byThe IEEE1588 clock recovering;
Described second clock is the system works clock of IEEE1588 processor or physical interface.
9. equipment according to claim 6, is characterized in that, of described second clockOne frequency is three times or above multiple of the first frequency of described the first clock.
10. equipment according to claim 9, is characterized in that, described first frequency is25MHz, described second frequency is 125MHz.
11. equipment according to claim 6, is characterized in that, also comprise:
-receiving element, for receiving the timestamp request of self processor;
-provide unit, for up-to-date described timestamp is provided to described processor.
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| CN201110159174.9A CN102833024B (en) | 2011-06-14 | 2011-06-14 | Method and the equipment of generation time stamp |
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| CN201110159174.9A CN102833024B (en) | 2011-06-14 | 2011-06-14 | Method and the equipment of generation time stamp |
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| CN102833024B true CN102833024B (en) | 2016-05-25 |
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Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108121675A (en) * | 2017-12-04 | 2018-06-05 | 北京信而泰科技股份有限公司 | Timestamp synchronous method and device between different clock-domains |
| US10778360B1 (en) | 2018-12-06 | 2020-09-15 | Xilinx, Inc. | High accuracy timestamp support |
| CN112953669B (en) * | 2019-12-11 | 2022-04-29 | 烽火通信科技股份有限公司 | Method and system for improving timestamp precision |
| WO2022160283A1 (en) * | 2021-01-29 | 2022-08-04 | 华为技术有限公司 | Sampling method, sampling circuit, and clock synchronization method of distributed network |
| CN113237465B (en) * | 2021-04-21 | 2022-06-07 | 中国科学院长春光学精密机械与物理研究所 | Timestamp generation method of high-precision mapping camera |
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| CN101893912A (en) * | 2009-05-22 | 2010-11-24 | 卓联半导体有限公司 | The clock circuit that is used for digital circuit |
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| US7113886B2 (en) * | 2002-01-23 | 2006-09-26 | Credence Systems Corporation | Circuit and method for distributing events in an event stream |
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| CN1722654A (en) * | 2004-12-31 | 2006-01-18 | 杭州华为三康技术有限公司 | Ethernet equipment time clock adjustment device |
| CN101741757A (en) * | 2008-11-21 | 2010-06-16 | 华为技术有限公司 | Message sending method and communication equipment |
| CN101893912A (en) * | 2009-05-22 | 2010-11-24 | 卓联半导体有限公司 | The clock circuit that is used for digital circuit |
| CN101887286A (en) * | 2010-07-09 | 2010-11-17 | 中兴通讯股份有限公司 | Method and device for converting time format |
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