CN102833024A

CN102833024A - Method and apparatus for generating timestamp

Info

Publication number: CN102833024A
Application number: CN2011101591749A
Authority: CN
Inventors: 黄华明
Original assignee: Alcatel Lucent Shanghai Bell Co Ltd
Current assignee: Nokia Shanghai Bell Co Ltd
Priority date: 2011-06-14
Filing date: 2011-06-14
Publication date: 2012-12-19
Anticipated expiration: 2031-06-14
Also published as: CN102833024B

Abstract

In order to solve the technical problems of serious delay and high hardware cost caused by the clock domain crossing transmission of timestamps in the prior art, the invention provides a method and apparatus for generating a timestamp. The apparatus comprises a first circuit, a second circuit, a detecting unit and a timestamp generating unit, wherein the first circuit is used for receiving a first clock, the second circuit is used for receiving a second clock, the detecting unit is used for detecting each rising edge of the first clock based on the second clock, the timestamp generating unit is used for controlling the timestamp to increase a time span corresponding to the cycle of the first clock when the detecting unit detects the rising edge. According to the invention, the timestamp is directly updated according to the rising edge of the first clock detected based on the second clock, so that the timestamp can relatively exactly indicate the variation of the first clock and mistakes are reduced; in addition, the timestamp with high data amount generated by the first clock is prevented from being transmitted and treated, in this way, the delay from the requiring of the timestamp to the obtaining of the timestamp is reduced, the difficulty of a system is lowered and the hardware cost is reduced.

Description

Method and equipment that generation time stabs

Technical field

Simultaneous techniques in the present invention relates to communicate by letter relates in particular to the generating technique of timestamp.

Background technology

In IEEE 1588v2 system, use at present the driving of the clock that recovers out by IEEE 1588 algorithms as the local time stamp counter.When the bag of PHY side arrived, the IEEE1588 processor can use this local time stamp counter, this bag is stamped the timestamp of due in.

In present IEEE 1588 systems, IEEE 1588 recovers, and to be used to drive the clock frequency of local time stamp counter lower, for example is 25MHz.Therefore, the local time stamp counter works is at the clock zone of 25MHz.But in system, phy interface and IEEE 1588 processors are the clock zones that are operated in 125MHz.Therefore, when system detects the bag of arrival and need obtain and timestamp is beaten when this is wrapped, this system must be with being delivered to 125MHz system clock territory by the timestamp of the clock generating of 25MHz from IEEE 1588 clock zones of 25MHz.In general, the length of timestamp is 80 bits.The principle of this technical scheme is as shown in Figure 1.

For this timestamp is delivered to 125MHz system clock territory from IEEE 1588 clock zones, two kinds of solutions are arranged in the industry at present: sampling voting method and asynchronous FIFO (FIFO) method.

In sampling voting method, the local time stamp maker is in the 25MHz clock zone, and in its 80 registers that each bit of timestamp that generates is deposited with respectively, each register has been deposited the logical value of each bit in 80 bits of timestamp one by one.Those registers are connected on 80 registers that are positioned at the 125MHz clock zone through logic respectively one by one.The clock of 125MHz drives and reads these 80 registers of 125MHz clock zone, thereby in the 125MHz clock zone, obtains timestamp.Because the line length of register differs between two territories, thus the time that the register in the 125MHz clock zone obtains actual value and difference possibly appear.Therefore, in sampling voting method, after IEEE 1588 processors receive the timestamp request; Use the clock of 125MHz; Each register to the 125MHz clock zone carries out repeatedly, for example three samplings, and respectively in 80 registers each; With at least two equal sampled values as the actual value of timestamp at this bit, thereby obtain the timestamp of 80 bits.Fig. 1 shows the sequential chart of sampling voting method.It is thus clear that owing to carried out repeatedly sampling, the time that obtains final voting result will be later than the time of timestamp request greatly.In general, as shown in Figure 2, IEEE 1588 processors request time in time 11 and 18 stabs, and voting result just produces and offer IEEE 1588 processors respectively in

time

12 and 19, produced certain delay.Under some extreme cases; For example for the timestamp request in the time among Fig. 2 13, it arrives at times 13 end of 25MHz clock, because next clock cycle of 25MHz clock arrives immediately; The register of 125MHz clock zone may be updated to next clock cycle time corresponding of 25MHz clock and stab; Because repeatedly voting may be adjudicated next clock cycle 14 time corresponding that obtains the 25MHz clock at the 125MHz clock zone and stabbed, this has just caused wrong generation.And sampling voting method also need take more resource.To adopt the ALTERA EP2AGX125EF29I5 voting method that realizes sampling to be example, as shown in Figure 3, need LUT (logical block table) and 325 special registers of using 91 to use as function generator.

In asynchronous FIFO (FIFO) method, the local time stamp maker is in the 25MHz clock zone, and its each bit with the timestamp that generates stores into respectively in the buffer (Buffer), and storing frequencies should be 25MHz.The output of this buffer is positioned at the 125MHz clock zone, receives the driving of 125MHz clock from this buffer, to read the timestamp that gets into buffer at first.But can there be certain delay in asynchronism first in first out method.As shown in Figure 4, IEEE 1588 processors request time in

time

11,13 and 18 stabs.In

identical time

11,13 and 18, produced response respectively.But the timestamp that obtains was respectively the timestamp of a

last time

10,12 and 17.The timestamp that is this moment can't be passed in the clock zone of 125MHz in time.And asynchronism first in first out method also need take more resource.To adopt ALTERA EP2AGX125EF29I5 to realize that asynchronous first-in first-out method is an example; As shown in Figure 5; Under the situation of using the M9K block RAM, need LUT (logical block table), 89 special registers and 4 M9K pieces of using 79 to use as function generator.As shown in Figure 6, under the situation of using MLAB RAM, LUT (logical block table) and 669 special registers of needing use 215 each and every one to use as function generator.

It is thus clear that all there is certain delay in the existing technology that obtains the timestamp that the 25MHz clock zone produces at the 125MHz clock zone, and these technology all need take more resource.

Summary of the invention

Therefore, a kind of technology that postpones little acquisition timestamp need be provided.Preferably, this technology also should take less resource, has lower design complexities.

According to an aspect of the present invention, the method that provides a kind of generation time to stab is characterized in that, comprises the steps:

-reception first clock;

-detect each rising edge of said first clock based on second clock;

-when detecting said rising edge, the control time is stabbed the time span that increases corresponding to the cycle of said first clock

In this aspect, timestamp has reduced mistake according to based on the rising edge of detected first clock of second clock and directly renewal makes timestamp can reflect the variation of first clock more exactly; And this aspect has been avoided the bigger timestamp of the data volume of first clock generating is transmitted and handles, and has reduced from request time and has stabbed the delay that obtains between the timestamp, has also reduced the system complex degree.

Preferred embodiment this method is the method that generation time stabs in the second clock territory according to one, and said receiving step receives said first clock from first clock zone in said second clock territory.

This preferred embodiment provides, and generation is specially adapted to the application scenario that the cross clock domain acquisition time stabs based on the method for the timestamp of first clock in the second clock territory.

According to another preferred embodiment, said first clock is the IEEE1588 clock that is resumed; Said second clock is the system works clock of IEEE 1588 processors or physical interface.

This preferred embodiment is applied in IEEE 1588 systems, has solved this system and need obtain the technical problem corresponding to the timestamp of IEEE 1588 clocks in the system clock territory.

According to another aspect of the present invention, the equipment that provides a kind of generation time to stab is characterized in that, comprising:

-the first circuit is used to receive first clock;

-the second circuit is used to receive second clock;

-detecting unit is used for detecting based on said second clock each rising edge of said first clock;

-timestamp generation unit is used for when said detection arrives said rising edge, and the control time is stabbed the time span that increases corresponding to the cycle of said first clock.

In this aspect, make timestamp can reflect the variation of first clock more exactly; And this aspect has been avoided the bigger timestamp of the data volume of first clock generating is handled, and has reduced from request time and has stabbed the delay that obtains between the timestamp.And this equipment need not take buffer, and logical block table and register that this aspect of experiment proof takies are also less.

According to one preferred embodiment, said first circuit is the single-bit circuit.

First clock that this preferred embodiment only needs to transmit single-bit need not transmit the for example timestamp of 80 bits, greatly reduces the complexity of equipment.

Other advantage of the present invention, aspect and characteristic will be described below, and are perhaps understood by those skilled in the art through the explanation of hereinafter

Description of drawings

To only the preferred embodiments of the present invention more specifically be described with reference to following accompanying drawing hereinafter through example:

Fig. 1 shows the schematic diagram that existing cross clock domain passing time stabs;

Fig. 2 shows existing sampling voting method, existing asynchronous first-in first-out method and separately sequential chart according to the embodiment of the present invention;

Fig. 3 shows the shared resource of existing sampling voting method;

Fig. 4 shows and uses M9K to realize the shared resource of existing asynchronous first-in first-out method;

Fig. 5 shows and uses MLAB to realize the shared resource of existing asynchronous first-in first-out method;

Fig. 6 shows the schematic diagram that stabs according to generation time of the present invention;

Fig. 7 shows the shared resource of equipment of stabbing according to generation time of the present invention.

In the accompanying drawing, same or analogous Reference numeral is represented same or analogous steps characteristic or parts (module) characteristic.

Embodiment

With reference to Fig. 7 to Fig. 9, method and apparatus according to the invention is detailed below.

Fig. 7 shows the schematic diagram that stabs according to generation time of the present invention, and equipment according to the present invention comprises:

-the first circuit is used to receive first clock, for example 25MHz IEEE 1588 clocks among Fig. 7;

-the second circuit is used to receive second clock, for example the 125MHz system clock among Fig. 7;

-detecting unit is used for detecting based on second clock each rising edge of first clock; And

-timestamp generation unit is used for whenever said detection during to the rising edge of first clock, and the control time is stabbed the time span that increases corresponding to the cycle of first clock.

Method according to generation time of the present invention stabs comprises the steps:

-reception first clock;

-detect each rising edge of said first clock based on second clock;

In general, 25MHz IEEE 1588 clocks itself are single-bit, as shown in Figure 8.Therefore; First circuit also is a single-bit; Just can accomplish the function of 25MHz IEEE 1588 clocks being introduced the detecting unit in the 125MHz system clock territory, and the 80 bit timestamps introducing 125MHz system clock territory that needn't as prior art, use the data/address bus of 80 bits in 25MHz IEEE 1588 clock zones, to produce.This execution mode has been simplified design, and has also reduced shared logical resource.

After 25MHz IEEE 1588 clocks were introduced into detecting unit, detecting unit detected each rising edge of first clock based on the 125MHz system clock.Concrete, detecting unit can be in each cycle of 125MHz system clock, and for example rising edge triggers, and detects the logical value of 25MHz IEEE 1588 clocks, i.e. level.If testing result is a low level in certain one-period of 125MHz system clock, and testing result is a high level in the following one-period that is right after, so just mean that there is a rising edge in 25MHz IEEE 1588 clocks.

After detecting rising edge, detecting unit can pass through a triggering signal, and for example pulse is stabbed generation unit with 25MHz IEEE 1588 clock generation rising edge notifying times.

When the timestamp generation unit received this triggering signal, the control time was stabbed the time span that increases corresponding to the cycle of 25MHz IEEE 1588 clocks, for example increases by 40 nanoseconds, and the timestamp after the increase is as up-to-date timestamp.This up-to-date timestamp can be deposited in the register of 80 bits.If this register realizes having deposited a last timestamp, so up-to-date timestamp covers information before.

For example, after first rising edge of IEEE 1588 clocks in Fig. 6 arrived, detection was to this rising edge.Because digital circuit is the relation that driven by the 125MHz system clock, the timestamp generation unit will generate the timestamp that increases progressively, i.e. time 11 when next 125MHz system clock arrives.With respect to delay of the prior art, as shown in Figure 6, delay of the present invention has obtained control significantly.And,, can this delay be reduced further through improving the frequency of clock.

In any moment in the time 11, for example the pairing moment of timestamp request among Fig. 6, IEEE 1588 processor request times stab, and the timestamp generation unit can offer IEEE 1588 processors with up-to-date timestamp immediately.For example, IEEE 1588 processors directly read 80 bit register and can obtain up-to-date timestamp.Therefore, this execution mode can for example offer IEEE 1588 processors with timestamp in time immediately, has reduced delay.

Afterwards, to each rising edge of IEEE 1588 clocks, more than operation repeats.As shown in Figure 6, timestamp is updated to 12,13 successively, 14.......In

time

13 and 18, IEEE 1588 processor requests and obtain corresponding timestamp immediately.

Consider the shared resource of the present invention, be example to adopt the ALTERA EP2AGX125EF29I5 voting method that realizes sampling, as shown in Figure 7, only need LUT (logical block table) and 66 special registers of using 65 to use as function generator.It is thus clear that with respect to prior art, the shared resource of the present invention is less.

Although in accompanying drawing and aforesaid description sets forth in detail with the present invention has been described, should think that this is illustrated and describes is illustrative and exemplary, rather than restrictive; The invention is not restricted to above-mentioned execution mode.

The those skilled in the art in those present technique fields can be through research specification, disclosed content and accompanying drawing and appending claims, and understanding and enforcement are to other changes of the execution mode of disclosure.In practical application of the present invention, the function of a plurality of technical characterictics of being quoted during a part possibility enforcement of rights requires.In claim, word " comprises " element and the step of not getting rid of other, and wording " one " is not got rid of plural number.Any Reference numeral in the claim should not be construed as the restriction to scope.

Claims

1. the method that generation time stabs is characterized in that, comprises the steps:

-reception first clock;

-detect each rising edge of said first clock based on second clock;

-when detecting said rising edge, the control time is stabbed the time span that increases corresponding to the cycle of said first clock.

2. method according to claim 1 is characterized in that, this method is the method that generation time stabs in the second clock territory, and said receiving step receives said first clock from first clock zone in said second clock territory.

3. method according to claim 1 and 2 is characterized in that, said first clock is IEEE 1588 clocks that are resumed;

Said second clock is the system works clock of IEEE 1588 processors or physical interface.

4. method according to claim 3 is characterized in that, the first frequency of said second clock is three times or an above multiple of the first frequency of said first clock.

5. method according to claim 4 is characterized in that, said first frequency is 25MHz, and said second frequency is 125MHz.

6. method according to claim 1 and 2 is characterized in that, also comprises the steps:

The timestamp request of-reception from processor;

-to said processor up-to-date said timestamp is provided.

7. the equipment that generation time stabs is characterized in that, comprising:

-the first circuit is used to receive first clock;

-the second circuit is used to receive second clock;

8. equipment according to claim 7 is characterized in that, said equipment work is in the second clock territory, and said first circuit receives said first clock from first clock zone.

9. according to claim 7 or 8 described equipment, it is characterized in that said first circuit is the single-bit circuit.

10. according to claim 7 or 8 described equipment, it is characterized in that said first clock is IEEE 1588 clocks that are resumed;

11., it is characterized in that the first frequency of said second clock is three times or an above multiple of the first frequency of said first clock according to claim 7 or 8 described equipment.

12. equipment according to claim 11 is characterized in that, said first frequency is 25MHz, and said second frequency is 125MHz.

13. according to claim 7 or 8 described equipment, it is characterized in that, also comprise:

-receiving element is used to receive the timestamp request of from processor;

-unit is provided, be used for up-to-date said timestamp being provided to said processor.