CN103516455A - Data synchronism method and device - Google Patents
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- CN103516455A CN103516455A CN201210207815.8A CN201210207815A CN103516455A CN 103516455 A CN103516455 A CN 103516455A CN 201210207815 A CN201210207815 A CN 201210207815A CN 103516455 A CN103516455 A CN 103516455A
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Abstract
The embodiment of the invention provides a data synchronism method and a device. The method comprises the following steps: 1:N demultiplexing is conducted on inputted data by the utilization of a set asynchronous clock to obtain N-path data with transmission rate being 1/N of transmission rate of the inputted data and a first synchronizing signal with cycle being 2N of the cycle of the asynchronous clock; delay is conducted on the first synchronizing signal by the utilization of a set synchronous clock to obtain a second synchronizing signal and a third synchronizing signal; whether the second synchronizing signal is equal to the third synchronizing signal is determined at each sampling edge of the synchronized clock and an edge trigger signal is generated to carry out count operation; and sampling is conducted successively on the N-path data by the utilization of the synchronized clock and each outputted count value so as to obtain N:1 multiplexing output data. According to the invention, the problems of high RAM resource requirement and long delay time are solved.
Description
Technical field
The present invention relates to digital signal transmission field, relate in particular to a kind of synchronous method of data and device.
Background technology
Along with the scale of digital system is increasing, complexity is more and more higher, the application of two or more clock zones in logical design is more and more.In different clock zones, inevitably can run into the mutual transmission of data.Owing to can having certain phase difference and frequency jitter in short-term between two different clocks, in order to make the data can transmitting, when designing, the impact of ordered pair function in the time of must taking into full account, otherwise can shine into two failure of data synchronization between clock zone.
At present, data are transformed into synchronous clock domains by asynchronous clock domain adopts the method for double-interface RAM buffer data to realize conventionally: the clock of writing with asynchronous clock as dual port RAM, write the write address of clock generating dual port RAM, by writing clock at a port data writing; Again with synchronised clock as reading clock, and the address of reading that produces dual port RAM, reads clock in another port sense data; This dual port RAM degree of depth is that the scope of frequency difference in short-term of tolerating is as required determined.Respectively read/write address sampled with synchronised clock and compare, to judge whether the distance between read/write address is less than the minimum range that reading and writing conflict may occur, i.e. " risk distance ", if, the redirect of Ze Jiangdu address, forwards to behind current location address farthest, then carries out read operation; Otherwise needn't adjust, read address, directly carry out read operation.
The data that read out through said method, although can reach not only stable but also correct, can also shield phase difference between asynchronous clock and local synchronous clock and frequency jitter problem in short-term, the data that can realize asynchronous clock domain are synchronous, but the method for utilization, need to rely on the RAM resource of programmable logic device, in addition, the delay time of synchrodata is longer, need to be determined by the projected depth of dual port RAM.
Summary of the invention
The embodiment of the present invention provides a kind of synchronous method of data and device, in order to solve problem higher to the depth requirements of RAM in available data simultaneous techniques and that delay time is longer.
Based on the problems referred to above, a kind of synchronous method of data that the embodiment of the present invention provides, comprising:
The asynchronous clock of utilize setting carries out 1:N demultiplexing to the data of input, obtains every road transmission rate and be the first synchronizing signal that the N circuit-switched data of 1/N of data of input and cycle are 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, described the second synchronizing signal and described the 3rd synchronizing signal differ at least one synchronised clock cycle;
Each sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and judging for the first time when unequal, generation is along triggering signal and be counted as the first numerical value of setting, and according to the cycle of synchronised clock, proceed counting after being counted as the first numerical value of setting, on generating, once whether the numerical value along a counting in the moment judgement of triggering signal is the second value of setting, and if so, proceeds counting; If not, be counted as the first numerical value of described setting; The numerical value that output is counted at every turn successively;
Utilize the numerical value of each counting of described synchronised clock and output, successively described N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
The synchronous device of a kind of data that the embodiment of the present invention provides, comprising:
Demultiplexing module, for utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, obtain every road transmission rate and be the first synchronizing signal that the N circuit-switched data of 1/N of data of input and cycle are 2N asynchronous clock cycle, wherein N is greater than 1 integer;
Synchronization module, for utilizing the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal obtaining through described demultiplexing module, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle, with each the sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and generate along triggering signal when unequal;
Counting module, being used for receiving described synchronization module generates along triggering signal judging for the first time when unequal, and be counted as the first numerical value of setting, and according to the cycle of synchronised clock, proceed counting after being counted as the first numerical value of setting, described counting module receive that described synchronization module generates upper along the numerical value of a counting in the moment judgement of triggering signal, whether be once the second value of setting, if so, proceed counting; If not, be counted as the first numerical value of described setting; Described counting module is exported the numerical value of each counting successively;
Multiplexing module, for utilizing the numerical value of each counting of described synchronised clock and the output of described counting module, samples to described N circuit-switched data successively, obtains the multiplexing output data of N:1.
The beneficial effect of the embodiment of the present invention comprises: synchronous method and the device of data that the embodiment of the present invention provides, utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input obtains after N circuit-switched data and the first synchronizing signal, the synchronised clock that recycling is set postpones to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, then according to synchronised clock sampling edge, judge whether the second synchronizing signal and the 3rd synchronizing signal equate, generation is carried out counting operation along triggering signal, finally utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled and can be obtained synchrodata.The embodiment of the present invention can make the data of input generate after multichannel data at demultiplexing, according to two-way synchronizing signal is compared, flip-flop number is counted, according to the numerical value of counter, multichannel data is sampled and multiplexing output, reduced the time delay of transfer of data, avoided in available data simultaneous techniques, the RAM resource that need to rely on programmable logic device solves the synchronous problem of data, simultaneously, the synchronizing relay of data also can be controlled preferably, need to not decided by the projected depth of dual port RAM.
Accompanying drawing explanation
The flow chart of the method that data that Fig. 1 provides for the embodiment of the present invention are synchronous;
One of sequential chart of the data synchronization process that Fig. 2 provides for the embodiment of the present invention;
Two of the sequential chart of the data synchronization process that Fig. 3 provides for the embodiment of the present invention;
The structural representation of the device that data that Fig. 4 provides for the embodiment of the present invention are synchronous;
Synchronization module and the mutual schematic diagram of counting module that Fig. 5 provides for the embodiment of the present invention.
Embodiment
Below in conjunction with Figure of description, the method that a kind of data that the embodiment of the present invention is provided are synchronous and the embodiment of device describe.
A kind of synchronous method of data that the embodiment of the present invention provides, as shown in Figure 1, specifically comprises the following steps:
S101: the asynchronous clock of utilize setting carries out 1:N demultiplexing to the data of input, obtains every road transmission rate and is the first synchronizing signal that the N circuit-switched data of 1/N of data of input and cycle are 2N asynchronous clock cycle, and wherein N is greater than 1 integer.
Preferably, above-mentioned the first synchronizing signal can obtain by following manner:
Using the frame head position of any circuit-switched data after demultiplexing as rising edge or the trailing edge of the first synchronizing signal, using and be at least greater than 2 asynchronous clock cycles as the pulse duration of the first synchronizing signal, obtain the first synchronizing signal.
Particularly, in embodiments of the present invention, can adopt rising edge or the trailing edge of the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, in the process of demultiplexing, make the speed of the data of input drop to original 1/N.
As shown in Figure 2, asynchronous clock that take homology but that have transmission delay to change is example, suppose N=3, utilize the rising edge of asynchronous clock to carry out demultiplexing to 1 circuit-switched data (data A+ data B+ data C) of input, after demultiplexing, at the t1 moment, the t2 moment and t3, export respectively 3 circuit-switched data, i.e. data D constantly
0(the data A after corresponding speed reduces), data D
1(the data B after corresponding speed reduces) and data D
2(the data C after corresponding speed reduces); With t1 data D constantly
0for example, output data D
0time speed be in 1 circuit-switched data of original input data A 1/3;
In this process, also with data D
0frame head position as rising edge, take and be at least greater than the first synchronizing signal (sync) that cycle that 2 asynchronous clock cycles obtain as pulse duration is 6 asynchronous clock cycles.In embodiments of the present invention, for guarantee the synchronised clock of follow-up setting can reliable samples to data, the pulse duration of sync need at least be greater than 2 asynchronous clock cycles.
S102: utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, the second synchronizing signal and the 3rd synchronizing signal differ a synchronised clock cycle.
Preferably, the second synchronizing signal and the 3rd synchronizing signal obtain by following manner:
According to the rising edge of synchronised clock or trailing edge, the first synchronizing signal is postponed, obtain the second synchronizing signal;
A synchronised clock cycle of the second sync signal delay is obtained to the 3rd synchronizing signal.
As shown in Figure 2, adopt the trailing edge of synchronised clock to postpone the sync obtaining, at k0, constantly obtain the second synchronizing signal (sync1), sync1 is postponed to 1 synchronizing cycle and at k1, constantly obtain the 3rd synchronizing signal (sync2).
S103: on each sampling edge of synchronised clock, judge whether the second synchronizing signal and the 3rd synchronizing signal equate, and judging for the first time when unequal, generation is along triggering signal and be counted as the first numerical value of setting, and according to the cycle of synchronised clock, proceed counting after being counted as the first numerical value of setting, on generating, once whether the numerical value along a counting in the moment judgement of triggering signal is the second value of setting, and if so, proceeds counting; If not, be counted as first of setting and set numerical value; The numerical value that output is counted at every turn successively.
Preferably, the above-mentioned M digit counter that can utilize is counted, wherein
the value that is M is log
2on N, round.
In above-mentioned steps S103, each sampling that adopts synchronised clock, along judging for the first time sync1 and sync2 when unequal, generates along triggering signal, at this constantly, counter starts counting, is counted as the first numerical value of setting, and the first numerical value refers to that counter starts the numerical value of counting.In embodiments of the present invention, counter can carry out accumulated counts from 0 to N-1, also can carry out countdown from N-1 to 0, can also count since 2 or 3 etc., and the first numerical value of setting can be 0,2,3 or N-1 etc.
Particularly, when practical application, for fear of loss of clock or burr, can cause the slip of exporting data, in the upper moment once generating along triggering signal, can last count value be judged, if judge the second value of last count value for setting, counter need not be adjusted, continuation was counted according to the count cycle (the synchronised clock same period) cumulative (or successively decreasing), and if not the second value of setting, rolling counters forward is the first numerical value of setting.In this bright embodiment, the second value of setting be for follow-up generation along moment of triggering signal on numerical value that once count value of counter judges, the value of second value can be selected flexibly, for example, the second value of setting can be 2, can be also 5,6 or 0.In embodiments of the present invention, the first numerical value of setting and the second value of setting can be identical, also can be different.
As shown in Figure 2, suppose N=3, M=2, adopt 2 digit counters to count, in Fig. 2, suppose that the first numerical value of setting is 0, be that counter is since 0 counting, the second value of setting is 2, and in the y0 moment producing along triggering signal, judging last count results is 2, be the second value of setting, this hour counter is proceeded counting, is counted as 0, follow-uply at y1, y2 and y3, constantly exports respectively 1,2 and 0.
S104: utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
Preferably, the embodiment of the present invention can utilize synchronised clock from arbitrary count value, successively N circuit-switched data is sampled, and obtains the multiplexing output data of N:1.
As shown in Figure 2, at y0 time trigger counter, be output as 0, synchronised clock is constantly sampled as 0 to counter at y1, according to 0 couple of data D of count value
0sampling output (one piece of data A); At y2 constantly, according to 1 couple of data D of count value
1sampling output (one piece of data B); At y3 constantly according to 2 couples of data D of count value
2sampling output (one piece of data C).Concrete sampling process belongs to prior art, does not repeat them here.
Above-mentioned Fig. 2 be take the explanation that N=3 carries out the embodiment of the present invention as example, for comprising D (0), D (1) ... D (N-1) multiple segment data utilizes asynchronous clock the data of input to be carried out to the situation of 1:N demultiplexing, as shown in Figure 3, asynchronous clock adopts rising edge to process, at t0, constantly input data are started to demultiplexing, after demultiplexing, when ensuing t1, be carved into respectively t (N) N the clock cycle constantly, export respectively D
0, D
1, D
2... .D
n-1data after the demultiplexing of N road altogether, the speed of every circuit-switched data is originally to input the 1/N of data, it is the cycle that synchronizing signal sync be take 2N asynchronous clock width, in t0 moment saltus step, and D
0frame head aligned in position.By sync and synchronised clock, the synchronizing signal sync1 after being postponed and sync2, by both relatively after, rolling counters forward is 0,1,2 ... N-1, according to the value of rolling counters forward respectively to D
0, D
1, D
2... .D
n-1sample, multiplexing output data.D (0),, D (1) ' ... data and D
0, D
1, D
2... .D
n-1the synchronous method of data is similar.
Based on same inventive concept, the embodiment of the present invention also provides a kind of data synchronous device, the method that the principle of dealing with problems due to this device is synchronizeed with aforementioned data is similar, so the enforcement of this device can, referring to the enforcement of preceding method, repeat part and repeat no more.
As shown in Figure 4, the embodiment of the present invention provides data synchronous device, comprising:
Preferably, demultiplexing module 401 is specifically for usining the frame head position of any circuit-switched data after demultiplexing as rising edge or the trailing edge of the first synchronizing signal, using and be at least greater than 2 asynchronous clock cycles as the pulse duration of the first synchronizing signal, obtain the first synchronizing signal.
Preferably, synchronization module 402, specifically for according to the rising edge of synchronised clock or trailing edge, the first synchronizing signal being postponed, obtains the second synchronizing signal; A synchronised clock cycle of the second sync signal delay is obtained to the 3rd synchronizing signal.
Preferably, counting module 403 is
counter.
In embodiments of the present invention, synchronization module 402 in the specific implementation, can the signal synchronization unit 501(by as shown in Figure 5 generate two-way synchronizing signal sync1 and sync2), judging unit 502(judges whether to equate to two-way synchronizing signal) and M digit counter 403 realize, certainly, the embodiment of the present invention is also not limited to this kind of concrete structure zoned format.
Preferably, Multiplexing module 404 can utilize synchronised clock from arbitrary count value, successively N circuit-switched data is sampled, and obtains the multiplexing output data of N:1.
Synchronous method and the device of data that the embodiment of the present invention provides, utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input obtains after N circuit-switched data and the first synchronizing signal, the synchronised clock that recycling is set postpones to obtain the second synchronizing signal and the 3rd synchronizing signal to the first synchronizing signal, then according to synchronised clock sampling edge, judge whether the second synchronizing signal and the 3rd synchronizing signal equate, generation is carried out counting operation along triggering signal, finally utilize the numerical value of each counting of synchronised clock and output, successively N circuit-switched data is sampled and can be obtained synchrodata.The embodiment of the present invention can make the data of input generate after multichannel data at demultiplexing, according to two-way synchronizing signal being compared to the count value of generation, to multichannel data sampling synchronous output, reduced the time delay of transfer of data, avoided in available data simultaneous techniques, the RAM resource that need to rely on programmable logic device solves the synchronous problem of data, simultaneously, the synchronizing relay of data also can be controlled preferably, need to not decided by the projected depth of dual port RAM.
Obviously, those skilled in the art can carry out various changes and modification and not depart from the spirit and scope of the present invention the present invention.Like this, if within of the present invention these are revised and modification belongs to the scope of the claims in the present invention and equivalent technologies thereof, the present invention is also intended to comprise these changes and modification interior.
Claims (8)
1. the synchronous method of data, is characterized in that, comprising:
The asynchronous clock of utilize setting carries out 1:N demultiplexing to the data of input, obtains every road transmission rate and be the first synchronizing signal that the N circuit-switched data of 1/N of data of input and cycle are 2N asynchronous clock cycle, and wherein N is greater than 1 integer;
Utilize the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle;
Each sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and judging for the first time when unequal, generation is along triggering signal and be counted as the first numerical value of setting, and according to the cycle of synchronised clock, proceed counting after being counted as the first numerical value of setting, on generating, once whether the numerical value along a counting in the moment judgement of triggering signal is the second value of setting, if, proceed counting, if not, be counted as the first numerical value of described setting; The numerical value that output is counted at every turn successively;
Utilize the numerical value of each counting of described synchronised clock and output, successively described N circuit-switched data is sampled, obtain the multiplexing output data of N:1.
2. the method for claim 1, is characterized in that, the first synchronizing signal obtains by following manner:
Using the frame head position of any circuit-switched data after demultiplexing as rising edge or the trailing edge of the first synchronizing signal, using and be at least greater than 2 asynchronous clock cycles as the pulse duration of the first synchronizing signal, obtain described the first synchronizing signal.
3. the method for claim 1, is characterized in that, utilizes the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal, comprising:
According to the rising edge of described synchronised clock or trailing edge, described the first synchronizing signal is postponed, obtain described the second synchronizing signal;
A synchronised clock cycle of described the second sync signal delay is obtained to described the 3rd synchronizing signal.
4. the method for claim 1, is characterized in that, utilizes M digit counter to count, wherein
5. the synchronous device of data, is characterized in that, comprising:
Demultiplexing module, for utilizing the asynchronous clock of setting to carry out 1:N demultiplexing to the data of input, obtain every road transmission rate and be the first synchronizing signal that the N circuit-switched data of 1/N of data of input and cycle are 2N asynchronous clock cycle, wherein N is greater than 1 integer;
Synchronization module, for utilizing the synchronised clock of setting to postpone to obtain the second synchronizing signal and the 3rd synchronizing signal to described the first synchronizing signal obtaining through described demultiplexing module, described the second synchronizing signal and described the 3rd synchronizing signal differ a synchronised clock cycle, with each the sampling edge at described synchronised clock, judge whether described the second synchronizing signal and described the 3rd synchronizing signal equate, and generate along triggering signal when unequal;
Counting module, being used for receiving described synchronization module generates along triggering signal judging for the first time when unequal, and be counted as the first numerical value of setting, and according to the cycle of synchronised clock, proceed counting after being counted as the first numerical value of setting, described counting module receive that described synchronization module generates upper along the numerical value of a counting in the moment judgement of triggering signal, whether be once the second value of setting, if so, proceed counting; If not, be counted as the first numerical value of described setting; Described counting module is exported the numerical value of each counting successively;
Multiplexing module, for utilizing the numerical value of each counting of described synchronised clock and the output of described counting module, samples to described N circuit-switched data successively, obtains the multiplexing output data of N:1.
6. the synchronous device of data as claimed in claim 5, it is characterized in that, described Multiplexing module, specifically for usining the frame head position of any circuit-switched data after demultiplexing as rising edge or the trailing edge of the first synchronizing signal, using and be at least greater than 2 asynchronous clock cycles as the pulse duration of the first synchronizing signal, obtain described the first synchronizing signal.
7. the synchronous device of data as claimed in claim 5, is characterized in that, described synchronization module, specifically for according to the rising edge of described synchronised clock or trailing edge, described the first synchronizing signal being postponed, obtains described the second synchronizing signal; A synchronised clock cycle of described the second sync signal delay is obtained to described the 3rd synchronizing signal.
8. the synchronous device of data as claimed in claim 5, is characterized in that, described counting module is that figure place is
counter.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106897233A (en) * | 2015-12-17 | 2017-06-27 | 格科微电子（上海）有限公司 | The television mains-hold circuit of data transmission interface |
| CN105515752B (en) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of data synchronization for eliminating network clocking deviation |
| CN111740829A (en) * | 2020-08-03 | 2020-10-02 | 北京中创为南京量子通信技术有限公司 | Synchronization method and device of quantum key distribution system |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834683A (en) * | 2010-03-24 | 2010-09-15 | 珠海市佳讯实业有限公司 | Device for realizing fixed forwarding delay of V.24 interface multiplexer |
| CN102204204A (en) * | 2011-05-20 | 2011-09-28 | 华为技术有限公司 | A method for realizing pulse synchronization and a device thereof |
| WO2011134251A1 (en) * | 2010-04-30 | 2011-11-03 | 中兴通讯股份有限公司 | Method and system for synchronously transmitting asynchronous data |
-
2012
- 2012-06-21 CN CN201210207815.8A patent/CN103516455B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101834683A (en) * | 2010-03-24 | 2010-09-15 | 珠海市佳讯实业有限公司 | Device for realizing fixed forwarding delay of V.24 interface multiplexer |
| WO2011134251A1 (en) * | 2010-04-30 | 2011-11-03 | 中兴通讯股份有限公司 | Method and system for synchronously transmitting asynchronous data |
| CN102204204A (en) * | 2011-05-20 | 2011-09-28 | 华为技术有限公司 | A method for realizing pulse synchronization and a device thereof |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105515752B (en) * | 2015-12-07 | 2018-04-20 | 中国航空工业集团公司西安航空计算技术研究所 | A kind of method of data synchronization for eliminating network clocking deviation |
| CN106897233A (en) * | 2015-12-17 | 2017-06-27 | 格科微电子（上海）有限公司 | The television mains-hold circuit of data transmission interface |
| CN106897233B (en) * | 2015-12-17 | 2021-06-18 | 格科微电子（上海）有限公司 | Source synchronous circuit of data transmission interface |
| CN111740829A (en) * | 2020-08-03 | 2020-10-02 | 北京中创为南京量子通信技术有限公司 | Synchronization method and device of quantum key distribution system |
| CN111740829B (en) * | 2020-08-03 | 2020-12-04 | 北京中创为南京量子通信技术有限公司 | Synchronization method and device of quantum key distribution system |
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Address after: Room 401, building 12, east area, airport business park, No. 80, Huanhe North Road, free trade zone (Airport Economic Zone), Binhai New Area, Tianjin 300000 Patentee after: Gaoxing Zhilian Technology Co.,Ltd. Address before: 300308, Zhongxing Industrial base, 2 East seven, Airport Economic Zone, Tianjin Binhai New Area Patentee before: ZTE INTELLIGENT IOT TECHNOLOGY Co.,Ltd. |
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Address after: Room 401, building 12, East Airport Business Park, 80 Huanhe North Road, Tianjin Binhai New Area pilot free trade zone (Airport Economic Zone) Patentee after: Zte Intelligent Iot Technology Co.,Ltd. Address before: Room 401, building 12, East Airport Business Park, 80 Huanhe North Road, Tianjin Binhai New Area pilot free trade zone (Airport Economic Zone) Patentee before: Gaoxing Zhilian Technology Co.,Ltd. |
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| CP01 | Change in the name or title of a patent holder |