JP2000115147A - Asynchronous absorption circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely transfer signals between circuits operated by different clock frequencies and to surely prevent the propagation of a metastable state. SOLUTION: This asynchronous absorption circuit is provided with a first signal generation circuit part 2 for inputting prescribed signals and a first clock and generating a first signal synchronized with the first clock, a second signal generation circuit part 3 for inputting the first signal and the second clock of a frequency higher than the first clock and generating a second signal synchronized with the second clock, a third signal generation circuit part 4 for inputting the second signal and the second clock and generating a third signal synchronized with the second clock and a forth signal generation circuit part 5 for inputting the second signal and the third signal and generating a period where both signals are in different states as a forth signal. Also it can be provided with a forth change signal generation circuit part for inputting the third signal and the second clock and generating a forth change signal synchronized with the second clock and a fifth signal generation circuit part for inputting the third signal and the forth change signal and generating the period where both signals are in the different states as a fifth signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an asynchronous absorption circuit which is preferably applied when data such as video and audio are transmitted to a terminal such as a network display and displayed.

[0002]

2. Description of the Related Art Conventionally, when transmitting video and audio data to a terminal such as a network display for display, a clock frequency on a transmitting side and a clock frequency on a receiving side are synchronized. However, when synchronizing, a predetermined clock frequency is frequency-divided and used as the other clock frequency so that they match each other, so that the timing is adjusted or the transmission side and the reception side establish synchronization and then transmit.

When synchronizing by dividing a predetermined clock frequency, the network display cannot freely change the clock frequency depending on the size of the display unit and the like, and an optimum display can be obtained. It will be difficult. Further, in order to synchronize, negotiation between the transmitting side and the receiving side, establishment of synchronization timing, and the like are necessary, and the transmission / reception speed is reduced. For this reason, it is not preferable to a network display that requires a quick start-up and a smooth display.

[0004]

In the prior art, it is not possible to asynchronously connect two circuits having different clock frequencies. For this reason, the inventor has devised an asynchronous absorption circuit 71 as shown in FIG. The asynchronous absorption circuit 71 sends a signal A from a circuit 72 operating at a clock frequency A (hereinafter referred to as CLKA) to a circuit 73 operating at a clock frequency B (hereinafter referred to as CLKB).
(Hereinafter referred to as SIGA), and a signal B (hereinafter referred to as SIGB) is obtained by the circuit 73.

The asynchronous absorption circuit 71 includes a register 74
To extract SIGA, put the SIGA and CLKB into the register 75, and extract SIGB. Specifically, as shown in the time chart of each signal shown in FIG. 16, for example, a signal O (hereinafter referred to as S
(Referred to as IGO) into the register 74, the SIGO is caught by CLKA. That is, CLKA
Of SIGO at the time of rising of "1" (= 1H
If (IGH), SIGA becomes "1", and SIGA is kept at "1" until the next CLKA.

At the next rising edge of CLKA, if SIGO is "0" (= LOW), as shown in FIG. 16, SIGA switches from "1" to "0". If SIGO is at "1" even at the next rising edge of CLKA, SIGA continues to be at "1". In this way, SIGO serving as a reset signal
Are output from the circuit 72 as SIGA.

Next, the SIGA is put into the register 75 of the circuit 73, and the SIGB synchronized with the CLKB is extracted by the CLKB. This synchronization by CLKB is
This is performed in the same manner as in the previous CLKA. That is, CLK
The state of the SIGA at the time of the rise of B is detected.
Is “1” (= HIGH), SIGB becomes “1”,
If it is “0” (= LOW), it switches from “1” to “0”. This makes it possible to obtain SIGB synchronized with CLKB, although slightly delayed in time from SIGO.

However, when the circuit 72 operates at a frequency of 10 MHZ, for example,
When sending SIGA to the circuit 73 operating at a frequency of 23 MHz, at the timing shown in FIG.
Although the signal has a magnitude that rises twice, it becomes four times or twice at other timings, and the width of the SIGB differs depending on the time. When this happens,
Normal operation cannot be guaranteed. That is, if CLKB rises many times and the frequency changes each time, the circuit 75 operates in an unstable manner.

In the case where CLKB is slightly higher than CLKA, as shown in FIG.
And the timing of CLKB, SIGB becomes the rising width of two CLKBs as shown by the solid line.
As shown by the dashed line, the rising width may be three CLKBs. When such a state occurs, the operation of the circuit 73 becomes unstable. Further, as shown in FIG.
When CLKB has a smaller frequency than KA, a signal is constantly dropped.

[0010] When signals are exchanged asynchronously, as shown in FIG.
If CLKB rises during the transition from (= LOW) to “1” (= HIGH), a phenomenon called a so-called metastable state may occur in SIGB. This metastable state is a state in which power consumption becomes extremely large when SIGB is neither "0" nor "1". It should be noted that this metastable state means that if the cycle of CLKB is about 20 ns, 10
It lasts for about ns and then settles to "0" or "1". However, the large consumption of power in the metastable state poses a serious problem for portable terminals such as network computers, and parts are destroyed when a large current flows through the circuit section.

SUMMARY OF THE INVENTION An object of the present invention is to provide an asynchronous absorption circuit capable of reliably transmitting and receiving signals between circuits operating at different clock frequencies in view of the above-mentioned problems. Still another object of the present invention is to provide an asynchronous absorption circuit that can reliably prevent metastable state propagation.

[0012]

In order to achieve the above object, in the asynchronous absorption circuit according to the first aspect, a predetermined signal and a first clock are inputted, and the first clock rises or falls. A first signal generation circuit unit that generates a first signal synchronized with the first clock, and a first signal and a second clock having a higher frequency than the first clock. A second signal generation circuit unit that generates a second signal synchronized with the second clock by using the rising or falling of the second clock;
The second signal and the second clock are input and the second
A third signal generation circuit for generating a third signal synchronized with the second clock by using the rising or falling edge of the second clock, and inputting the second signal and the third signal to both signals. And a fourth signal generation circuit that generates a period in which the signals are in different states as a fourth signal.

Since a plurality of signal generation circuit units acting as registers are provided on the receiving side for receiving the first signal as described above, a signal of a predetermined magnitude can always be generated in synchronization with the second clock. Therefore, the operation of the circuit portion operated by the second clock can be performed normally.

Further, in the asynchronous absorption circuit according to the second aspect, a predetermined signal and a first clock are input, and the rising or falling of the first clock is used to input the predetermined signal and the first clock.
A first signal generation circuit for generating a first signal synchronized with the first clock; a first signal and a second clock having a higher frequency than the first clock; Using the clock rise or fall,
A second signal generation circuit for generating a second signal synchronized with the second clock, and inputting the second signal and the second clock to use the rise or fall of the second clock And a third signal generation circuit for generating a third signal synchronized with the second clock, and using the rising or falling of the second clock by inputting the third signal and the second clock. And a fourth change signal generation circuit section that generates a fourth change signal synchronized with the second clock;
A fifth signal for inputting the third signal and the fourth change signal and generating a period in which both signals are in different states as a fifth signal
A signal generation circuit section.

For this reason, at least three register-like signal generation circuit units operated by the second clock are provided, so that when the signal is input from the first signal generation circuit unit to the second signal generation circuit unit, the second signal generation circuit unit is used. Even if the metastable state occurs in the signal generation circuit, the metastable state can be confined only in the second signal generation circuit. As a result, propagation of the metastable state can be suppressed, and an increase in power consumption can be suppressed.

Further, according to the third aspect of the present invention, in the asynchronous absorption circuit according to the first or second aspect, a circuit unit corresponding to a second signal generation circuit unit which takes a synchronization signal with respect to an input signal is provided. At least one is provided between the second signal generation circuit unit and the third signal generation circuit unit.

As described above, since at least one circuit unit similar to the second signal generation circuit unit is added, normal operation of the circuit and prevention of propagation of the metastable state can be performed more reliably.

Further, the asynchronous absorption circuit according to claim 4 is
A first clock in which the cycle width of the first clock is smaller than a cycle width obtained by doubling the cycle width of the second clock is used, and each cycle width of the predetermined signal and the first clock is increased by n times ( Frequency dividing means for dividing (n is an integer of 2 or more) is provided on the front side of the first signal generation circuit unit.

As described above, since the clock frequency is divided, even if the cycle width of the first clock is smaller than twice the cycle width of the second clock, the circuit operating at a different clock frequency can be used. The signal can be reliably exchanged.

Further, in the asynchronous absorption circuit according to the fifth aspect, a predetermined signal and a first clock are input, and the rising or falling of the first clock is used to input the predetermined signal and the first clock.
A first signal generation circuit for generating a first signal synchronized with the first clock; and a second signal having a higher frequency than the first signal and the first clock.
A second signal generation circuit unit that generates a second signal synchronized with the second clock by using the rising or falling of the clock of the second clock. A first clock which is smaller than a cycle width obtained by doubling a cycle width of the clock is used, and
After the signal generation circuit section, the state of the first signal based on the first clock is distributed every m (m is an integer of 1 or more) with respect to the first clock to generate m + 1 signals. A circuit is provided, and each signal by this distribution circuit is input to a circuit section similar to the (m + 1) first signal generation circuit sections, and each signal is processed by the asynchronous absorption circuit according to any one of claims 1 to 3. ing.

As described above, since the output signal is distributed to a plurality of circuits and output to an asynchronous circuit having a different clock frequency, the output signal is not heavy in circuit as in frequency division, and is compatible with various clock frequencies. can do.

The asynchronous absorption circuit according to the present invention has a second circuit for receiving a video signal sent from the first circuit, and a display means for displaying an image based on a display signal from the second circuit. Then, in an asynchronous absorption circuit for an image display device in which the current display area based on the display signal is smaller than the virtual display area based on the video signal, the display signal is fed back to the first circuit, and the image data in the video signal is reduced. If it does not appear in the current display area, the image data is
Is not sent to the circuit.

As described above, since the signal on the output side is controlled according to the state of the circuit on the receiving side, image data can be transferred without problems even between asynchronous circuits.
Moreover, since the image data of the portion not displayed is not sent to the receiving side, no extra data is sent, and the display speed can be increased.

Further, in the asynchronous absorption circuit according to the present invention, a first circuit driven by a first clock and an interface circuit driven by a second clock receiving a video signal from the first circuit are provided. Circuit, a first counter provided in the first circuit, and a second counter provided in the second circuit.
The first counter counts the number of pixels in the video signal to be transmitted, counts the current pixel number to be received by the second counter, and counts the counter value of the second counter every time a predetermined number is reached. Then, a feedback signal is transmitted from the second circuit to the first circuit so that the number of transmission pixels and the number of reception pixels are synchronized.

As described above, since the second circuit, which operates at a clock different from the clock of the first circuit, sends a feedback signal as a control signal to the first circuit, the counter operates at a different clock. And so on operate almost synchronously. As a result, it becomes possible to synchronize image data and the like with other data.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. First, an asynchronous absorption circuit 1 according to the first embodiment will be described with reference to FIGS.

As shown in FIG. 1, the asynchronous absorption circuit 1 receives a video reset signal (hereinafter referred to as a signal 0) and a first clock frequency (hereinafter referred to as a clock A) as predetermined signals. A first register 2 serving as a first signal generation circuit for generating a signal A (hereinafter referred to as signal A), a signal A and a second clock frequency (hereinafter referred to as clock B), and a second signal (hereinafter referred to as signal B). ) That generates a third signal (hereinafter, referred to as a signal C) that receives a signal B and a clock B and generates a third signal (hereinafter, referred to as a signal C). It has a third register 4 and a fourth signal generation circuit section 5 which receives a signal B and a signal C and generates a fourth signal (hereinafter referred to as a signal D).

As shown in FIG. 2, the first register 2 stores the state of the signal O at the time of the rising of the clock A until the next rising of the clock A.
If the state of the signal O at the next rising of the clock A is the same as the previous state, the state is maintained, and if it is different, the state is inverted. Such an operation is the same for the second register 3 and the third register 4 as well as for the register 7 shown earlier.
4,75. In this embodiment, the clock A has a frequency of 6 MHz to 33 MHZ, and the clock B has a frequency of 50 MHZ. The signal O is a start-up signal (reset signal) of video data transmitted to the network display 10 described later. The clock A is a frequency that is changed according to the size of the display unit 11 of the network display 10, and the clock B is a clock frequency specific to the network display 10 described later.

The signal O in FIG. 2A becomes the signal A in FIG. And
The clock B and the signal A become the signal B by the second register 3. Until the signal B is generated, it is the same as the technique of FIGS. 15 and 16 described above. Thereafter, the signal B and the clock B are input to the third register 4. Then, a signal C which is delayed from the signal B by one cycle of the clock B is generated.

The signal C and the previously generated signal B are input to the fourth signal generation circuit 5. Then, the fourth
The signal generation circuit unit 5 generates a HIGH (= "1") signal only when the signal B is "1" and the signal C is "0". The fourth signal generation circuit section 5 generates a signal D which is such a signal.

Although the signal D is slightly delayed in time as compared with the signal O, it is reliably detected as one cycle of the clock B. Therefore, based on the signal (signal A) synchronized with the clock A, a signal (= signal D) synchronized with the clock B and always having the same width is generated.

The asynchronous absorption circuit 1 as described above is incorporated in a network display 10 as shown in FIG. The network display 10 includes a display unit 11 composed of a central liquid crystal, an operation unit 12 disposed around the display unit 11, a speaker unit 13 for outputting sound, and a magnetic unit capable of accessing a specific wavepage on the Internet. A magnetic card unit 14 into which a card is inserted and which reads its address or reads another magnetic card
And a connection section 15 connected to a current line, a personal computer serving as a host, and the like.

The left and right operation units 12 of the display unit 11 are 1-1
0, there are ten types of menu buttons 12, and each of these buttons 12a
An operation menu corresponding to the display unit 11 close to is displayed. For example, this network display 10
And various animations stored in a personal computer connected to the LAN by their numbers. That is, when the first menu book 12a is pressed, the first animation is reproduced. Various operation buttons 12b for accessing a homepage on the Internet are arranged below the display unit 11. An instruction operation unit 12c is provided near the magnetic card reader unit 14 to move the operation arrow on the screen up, down, left, and right.

Such a network display 10
Has the following circuit configuration. That is, as shown in FIG.
D (Liquid Crystal) Display Unit 11 and Control Unit CP
An instruction from a U memory (= central processing unit) 21, a dedicated graphics LSI 22, a program ROM 23, and an external information source 24 such as a personal computer is transmitted to the CPU memory 21 or transmitted from the CPU memory 21 to the personal computer. Data receiving and transmitting circuit 25, dedicated graphics LS
VRAM (video ram) 26 connected to I22 and sound circuit 2 for supplying sound to an external amplifier and speaker unit
7 and a display LSI 28 for driving and controlling the display 11
And a memory 29 for storing a display program and the like.

Here, the asynchronous absorption circuit 1 is provided between the dedicated graphics LSI 22 and the sound circuit 27, between the dedicated graphics CSI 22 and the display LSI 28, and the like. Note that the external information source 24 is outside the network display 10 and controls the display contents of the network display 10 at the extreme. In the program ROM 23, the CPU memory 21 receives specific data from a web browser or a display program, receives a program for controlling display, and receives a command from the external information source 24, and switches the display flow. And a program for performing processing for displaying the specified specific image at the specified specific position.

Here, the dedicated graphics LSI 22
Is controlled by the CPU memory 21 for controlling the sequence between the screens. On the other hand, for displaying a series of images and sprites on each screen, the program goes to a program or data in the memory 29 and is based on the program or data. , And a series of movements of the sprite and the like are controlled. Further, the VRAM 26 can take in two screens. Two screens are used because one screen is used for display and the other screen is used for writing. This two-screen method eliminates flickering during writing and improves image quality. The sound circuit 27 is an 8-bit, 8KHZ, one-channel sound circuit.
Other values can be used as appropriate.

Next, an asynchronous absorption circuit 30 according to a second embodiment will be described with reference to FIGS. This asynchronous absorption circuit 30 is used for the network display 10 as in the first embodiment.

The asynchronous absorption circuit 30 is a circuit that can completely prevent the influence of the metastable state even when it occurs. Basically, the asynchronous absorption circuit 30 is different from the asynchronous absorption circuit 1 of the first embodiment. It has a similar configuration. For this reason,
The same members as those in the first embodiment are denoted by the same reference numerals, and the same signals will be described using the same words, and detailed description thereof will be omitted or simplified. .

The asynchronous absorption circuit 30 includes a first register 2 to which the signal O and the clock A are inputted, a second register 3 to which the signal A and the clock B are inputted, and a third register 4 to which the signal B and the clock B are inputted. And a signal C and a clock B, and a fourth register 6 serving as a fourth change signal generation circuit for generating a fourth change signal (hereinafter, referred to as a signal E); a signal C and a signal E; A fifth signal generation circuit section 7 for generating a signal (hereinafter, referred to as a signal F). Here, the fifth signal generation circuit unit 7
Has the same function as the fourth signal generation circuit 5 of the first embodiment.

When the signal B is generated, the asynchronous absorption circuit 30 does not propagate the metastable state even if it occurs. That is, as shown in FIG. 6, even if the signal B is a signal including the metastable state portion 8 and the subsequent steady portion 9 settling to “1” or “0”, the signal B is generated at the next clock B. B is "1" or "0".
Therefore, the signal C and the signal E are both deterministic signals and signals that are shifted by one cycle of the clock B. In addition, as shown in FIG.
In this case, the signals C and E become solid lines, and therefore, the fifth signal generation circuit unit 7 outputs one cycle of the clock B to HIG.
The signal F which becomes H is generated. As a result,
Even if the metastable phenomenon occurs, a large amount of current does not flow through the circuit. Moreover, the signal F for one clock can be reliably generated based on the signal signal O. When the stationary portion 9 is “0”, the signal F is indicated by a dashed line. Next, an asynchronous absorption circuit 31 according to a third embodiment will be described with reference to FIGS.

This asynchronous absorption circuit 31 is used when the clock A and clock B used in the second asynchronous absorption circuit 30 have a higher frequency than the clock B. For example, if clock A is 20 MHZ and clock B is 15 MHZ,
In the asynchronous absorption circuit 30, when the signal O is knocked by the clock A, the signal A 'of FIG. 8H is formed. Thereafter, when the clock B tries to take the signal A', the signal of FIG. As in the case of the signal B ', it may not be possible to take a signal.

Asynchronous absorption circuit 3 of the third embodiment
Reference numeral 1 denotes a configuration in which a frequency dividing means 32 is provided on the upstream side of the asynchronous absorption circuit 30 according to the second embodiment. In the asynchronous absorption circuit 31, a signal O, which is an important signal such as the first part of a video signal, and a clock A are divided by a frequency dividing means 32 into
The frequency is doubled, and the signal O 'in FIG.
(D) Clock A 'is made. Then, the signal O 'and the clock A' are input to the first register 2 of the asynchronous absorption circuit 30 according to the second embodiment, a signal A is generated, and the signal is input to the second register 3. And
The signal A is hit by the clock B, and the signal B is generated. After that, the operation becomes the same as that of the asynchronous absorption circuit 30 of the second embodiment.

In this embodiment, for example, if one pixel is output in two clocks of the signal A in the first and second embodiments, in the third embodiment, Two pixels are taken out at once for two clocks. The frequency dividing means 22 may increase the signal O or the clock A to an integer multiple such as triple or quadruple other than double to reduce the frequency and widen the cycle width of the signal.

Next, based on FIG. 9 and FIG.
The asynchronous absorption circuit 41 according to the embodiment will be described.

In the asynchronous absorption circuit 41, a distribution circuit 42 is provided after the first register 2 shown in FIG. This is because if the frequency dividing means 32 is provided as in the case of the asynchronous absorption circuit 31 according to the third embodiment, the speed becomes slower in terms of the circuit, so that the frequency dividing means 32 cannot always be adopted. The same function as the means 32 is to be performed by the distribution circuit 42.

That is, the asynchronous absorption circuit 41 is basically used when the clock A has a higher frequency than the clock B. In other words, this is adopted when the cycle width of the clock A is smaller than the cycle width of the clock B. More specifically, both the asynchronous absorption circuit 41 and the asynchronous absorption circuit 31 described above are used when the cycle width of the clock A is smaller than the cycle width obtained by doubling the cycle width of the clock B. You. This is because the cycle width of clock A is
If the cycle width is larger than the doubled width, the pulse signal by the clock A can be reliably obtained as the pulse signal by the clock B. If this condition is not satisfied, the signal can be picked up by the clock B. This is because there is a risk of disappearing.

The asynchronous absorption circuit 41 distributes the signal A generated by the first register 2 to the state of the clock A at the even-numbered clock and the state of the odd-numbered clock by the distribution circuit 42. That is, as shown in FIG. 10, the signal in the odd-numbered state is the ODD signal 42a, and the signal in the even-numbered state is EDD.
The signal becomes the VEN signal 42b.

More specifically, the ODD signal 42a is
In the example shown by, it is the state of the odd-numbered signal A,
"10001 $", and the EVEN signal 42b indicates "0
01010 ‥ ”. Then, this state is input to the registers 43 and 44, which are the same circuit sections as the first signal generation circuit section 2, respectively.
(E) Signal AODD and signal AEV shown in (F)
It becomes EN. Each of the generated signals has a cycle width wider than the cycle width of the signal A.

The asynchronous absorption circuit 41 shown in FIG. 9 is an example in which the clock signal is divided into an odd number and an even number.
, The signal can be divided into n + 1 signals. For example, taking every third signal gives four signals,
The cycle width of each signal is quadrupled.

Next, based on FIG. 11 and FIG.
The asynchronous absorption circuit 51 according to the embodiment will be described.
This asynchronous absorption circuit 51 is incorporated in the network display 10 as in the first to fourth embodiments.

The asynchronous absorption circuit 51 comprises a first circuit 52 operated by a clock C, a second circuit 53 operated by a clock D having a clock frequency different from the clock C, and a display means 54 composed of liquid crystal or the like. It is mainly composed of
In this embodiment, a signal G, which is a video signal, is sent from the first circuit 52 to the second circuit 53. From the second circuit 53, a signal H serving as a display signal (including a control signal) is sent to the display means 54. The display means 54
The display unit 54a for displaying a display signal is provided. Also,
The signal H generated in the second circuit 53 is
As a control signal.

The signal G is a video signal capable of displaying the entire virtual display area 55 composed of 580 × 262 pixels. On the other hand, the signal H is a signal for displaying image data in the current display area 56 including 320 × 240 pixels. Then, when there is no image data in the signal H, that is, there is no image data in the current display area 56, while the image data 57
7 need not be sent to the second circuit 53. However, in the conventional one, it is transmitted as it is. This asynchronous absorption circuit 5
In 1, since the signal H is fed back to the first circuit 52, the image data 57 and other frame data can be prevented from being sent.

On the other hand, in the current display area 56, the last pixel 58 in the screen continues to be displayed in the next frame. Therefore, the signal G from the first circuit 52 operated by the clock C is controlled by the control signal based on the signal H, and can be synchronized with the signal H.
In addition, there is no need to perform extra transmission from the first circuit 52 to the second circuit 53.

Next, an asynchronous absorption circuit 61 of a sixth embodiment shown in FIGS. 13 and 14 will be described. Note that this asynchronous absorption circuit 61 is also incorporated in the network display 10 as in the first to fifth embodiments.

The asynchronous absorption circuit 61 includes a first circuit 62 operated by a clock E, a second circuit 63 operated by a clock F having a different frequency from the clock E, and a first circuit 62 provided in the first circuit 62. , A second counter 63a provided in the second circuit, and a display means 64. In this embodiment, the first circuit 62 outputs a signal J serving as a video signal to the second circuit 6.
3 and a signal K serving as a display signal is output from the second circuit 63 to the display means 64. Then, the signal K is fed back to the first circuit 62 as a control signal.

The signal J is the same as the signal G described above, and the signal K is the same as the signal H. Then, in the asynchronous absorption circuit 61, the number of pixels of the image data sent from the first circuit 62 is counted by the first counter 62a. On the other hand, in the second circuit 63, the number of transmitted pixels is counted by the second counter 63a. Then, every time one scan line in the virtual display area 55 ends,
That is, every time the second circuit 63 receives 580 pixels, it outputs a control signal to that effect to the first circuit 62. As a result, the first circuit 62 and the second circuit 63 are synchronized. Although feedback is preferably performed for each scanning line, feedback may be performed for every several lines or for the last pixel of the current display area.

If such a control signal is not provided, in this kind of circuit where it is necessary to keep outputting the same image with clocks of different frequencies, there is a high risk that the position of the image will be disturbed and the image will be strange. Become. However, in the asynchronous absorption circuit 61, the first circuit 62 is controlled based on the count value of the second counter 63a, that is, based on the second circuit 63. Both circuits 62 and 63 can keep outputting the same video. Therefore, the image displayed on the display means 64 becomes stable.

Each of the above embodiments is an example of a preferred embodiment of the present invention, but is not limited thereto, and various modifications can be made without departing from the gist of the present invention. is there. For example, each of the asynchronous absorption circuits 1, 3
The device in which 0, 31, 41, 51, 61 is incorporated may be another device such as a personal computer or a server instead of the network display 10.

When synchronizing, the falling edge of the clock signal may be used instead of the rising edge. further,
When generating the signal D serving as the fourth signal and the signal F serving as the fifth signal, the “period of different states” is a portion where two input signals do not overlap and the front side is extracted. However, the rear side of the non-overlapping portion may be taken out. Further, the present invention may be applied to a circuit that handles other data such as text data and graphic data, instead of a circuit that handles video data and audio data. That is, the present invention can be generally applied when data is exchanged between circuits having different clock frequencies.

[0060]

As described above, in the asynchronous absorption circuit described in each claim, data exchange between circuits operating at different clock frequencies can be handled in the same manner as in the case of synchronization while being asynchronous. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram of an asynchronous absorption circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart of each signal in the circuit of FIG.

FIG. 3 is an external perspective view of a network display in which the asynchronous absorption circuit of FIG. 1 is incorporated.

FIG. 4 is a block diagram of a circuit of the network display of FIG. 3;

FIG. 5 is a block diagram of an asynchronous absorption circuit according to a second embodiment of the present invention.

FIG. 6 is a timing chart of each signal in the circuit of FIG.

FIG. 7 is a block diagram of an asynchronous absorption circuit according to a third embodiment of the present invention.

FIG. 8 is a timing chart of each signal in the circuit of FIG. 7;

FIG. 9 is a block diagram of an asynchronous absorption circuit according to a fourth embodiment of the present invention.

FIG. 10 is a timing chart of each signal in the circuit of FIG. 9;

FIG. 11 is a block diagram of an asynchronous absorption circuit according to a fifth embodiment of the present invention.

FIG. 12 is a diagram showing a virtual display area and a current display area in the circuit of FIG. 11;

FIG. 13 is a block diagram of an asynchronous absorption circuit according to a sixth embodiment of the present invention.

14 is a diagram showing a virtual display area and a current display area in the circuit of FIG. 13, including a scan line.

FIG. 15 is a block diagram of an asynchronous absorption circuit studied by the present inventors.

16 is a timing chart of each signal in the circuit of FIG.

FIG. 17 is a timing chart illustrating an example in which the circuit of FIG. 15 performs an uneasy operation.

FIG. 18 is a timing chart for explaining another example in which the circuit of FIG. 15 performs an uneasy operation.

FIG. 19 is a timing chart illustrating an example of a case where the circuit of FIG. 15 performs an unstable operation and is in a metastable state.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Asynchronous absorption circuit 2 1st register (1st signal generation circuit unit) 3 2nd register (2nd signal generation circuit unit) 4 3rd register (3rd signal generation circuit unit) 5 4th signal generation circuit unit 6 4th Register (fourth change signal generation circuit unit) 7 Fifth signal generation circuit unit 10 Network display 11 Display unit 21 CPU memory 22 Dedicated graphics LSI 26 VRAM 27 Sound circuit 28 Display LSI 30 Asynchronous absorption circuit 31 Asynchronous absorption circuit 32 minutes Circumferential means 41 Asynchronous absorption circuit 42 Distribution circuit 51 Asynchronous absorption circuit 52 First circuit 53 Second circuit 54 Display means 55 Virtual display area 56 Current display area 61 Asynchronous absorption circuit 62 First circuit 62a First counter 63 First Second circuit 63a Second counter 64 Display means

Claims (7)

[Claims] 1. A method of inputting a predetermined signal and a first clock, and generating a first signal synchronized with the first clock using rising or falling of the first clock. 1 signal generating circuit section, the first signal and the second clock having a higher frequency than the first clock are input, and the second clock is generated by using the rising or falling of the second clock. A second signal generation circuit for generating a second signal synchronized with the second clock, and inputting the second signal and the second clock and utilizing the rising or falling of the second clock. A third signal generation circuit for generating a third signal synchronized with the second clock, and a period in which the second signal and the third signal are input and both signals are in different states. Fourth signal generation to generate as signal 4 An asynchronous absorption circuit, comprising: a circuit unit. 2. A method of inputting a predetermined signal and a first clock, and generating a first signal synchronized with the first clock by using rising or falling of the first clock. 1 signal generating circuit section, the first signal and the second clock having a higher frequency than the first clock are input, and the second clock is generated by using the rising or falling of the second clock. A second signal generation circuit for generating a second signal synchronized with the second clock, and inputting the second signal and the second clock and utilizing the rising or falling of the second clock. Inputting the third signal and the second clock to generate a third signal synchronized with the second clock; Using the fall, this A fourth change signal generation circuit for generating a fourth change signal synchronized with the second clock; and a fifth period in which the third signal and the fourth change signal are input and both signals are in different states. And a fifth signal generation circuit for generating the signal as a signal. 3. A circuit corresponding to a second signal generation circuit for taking a synchronization signal with respect to an input signal is provided between the second signal generation circuit and the third signal generation circuit. 3. The asynchronous absorption circuit according to claim 1, wherein said asynchronous absorption circuit is provided. 4. The method according to claim 1, wherein the first clock has a cycle width smaller than a cycle width obtained by doubling a cycle width of the second clock. 4. The asynchronous circuit according to claim 1, wherein frequency dividing means for multiplying each cycle width of said clock by n (n is an integer of 2 or more) is provided on the front side of said first signal generation circuit section. Absorption circuit. 5. A method of inputting a predetermined signal and a first clock, and generating a first signal synchronized with the first clock by using rising or falling of the first clock. 1 signal generating circuit section, the first signal and the second clock having a higher frequency than the first clock are input, and the second clock is generated by using the rising or falling of the second clock. A second signal generation circuit unit that generates a second signal synchronized with the clock of (a), wherein the cycle width of the first clock is smaller than a cycle width obtained by doubling the cycle width of the second clock. While using the first clock, after the first signal generation circuit section, the state of the first signal based on the first clock is changed every m units (m is 1) based on the first clock.
A distribution circuit for generating m + 1 signals in accordance with the above integer) is provided, and each signal by this distribution circuit is represented by m + 1
4. An asynchronous absorption circuit, wherein the signals are input to the same circuit units as the first signal generation circuit units, and each signal is processed by the asynchronous absorption circuit according to any one of claims 1 to 3. 6. A virtual circuit comprising a second circuit for receiving a video signal sent from the first circuit, and display means for displaying an image based on a display signal from the second circuit. In comparison, in an asynchronous absorption circuit for an image display device in which the current display area by the display signal is small, the display signal is fed back to the first circuit, and the image data in the video signal is displayed in the current display area. Wherein the image data is not sent to the second circuit if it does not appear in the asynchronous circuit. 7. A first circuit driven by a first clock, a second circuit serving as an interface circuit driven by a second clock for receiving a video signal from the first circuit, and the first circuit And a second counter provided in the second circuit, wherein the number of pixels in the video signal to be transmitted is counted by the first counter, and the number of current pixels to be received is calculated. The second circuit counts, and every time the counter value of the second counter reaches a predetermined number, a feedback signal is transmitted from the second circuit to the first circuit, and the number of transmission pixels and the number of reception pixels A non-synchronous absorption circuit for an image display device, characterized in that synchronization is achieved.