JP2001136412A - Gamma correction circuit for a plurality of video display devices - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the lightness and the color of a still picture from being changed by gamma correction in the case of displaying a gamma correction menu with respect to a display device displaying a plurality of video images including a still picture. SOLUTION: The display device that a plurality of video data are written in different areas in a memory 26, read as video data written in a memory area and a display section 18 displays a plurality of video images, is provided with a dynamic gamma correction section 28, a static gamma correction section 34 and a selector 36. The selector 36 outputs selectively video data corrected by the dynamic gamma correction section 28 or video data corrected by the static gamma correction section 34 to the display section 18 on the basis of a signal pointing out a moving picture display position of the display section 18, and the display section 18 displays the video image of the video data corrected by the static gamma correction section 34 as to still picture video image among a plurality of the displayed video images so that the still picture video image is not affected by the dynamic gamma correction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for writing video data of a plurality of video images including a moving image video and a still image video to different areas in a memory by a writing processing unit and writing the video data to the memory by a reading processing unit. The present invention relates to a gamma correction circuit used in a multiple video display device that reads video data of a plurality of videos as video data written in one memory area and displays a plurality of videos on a display unit. For example, the present invention relates to a gamma correction circuit used for a display device (also referred to as a multi-screen display device) that simultaneously displays a plurality of images such as a multi-channel application.

[0002]

2. Description of the Related Art As a thin and lightweight display device,
PDP using PDP (plasma display panel)
Attention has been focused on display devices and LCD display devices using LCD (liquid crystal display) panels. Conventionally, such a display device displays a plurality of images including a moving image image and a still image image, and performs a gamma correction process on these images. I was

In FIG. 9, reference numeral 10 denotes a processing unit in the memory space 1, 12 denotes a processing unit in the memory space 2, 14 denotes a multi-screen processing unit, 16 denotes a selector, and 18 denotes a PDP display unit. The processing unit 10 in the memory space 1 performs a process of writing and reading out the input video data V1 to and from the memory space 1 of the memory 11 having a built-in memory, thereby providing a predetermined data to the input video data V1. Perform processing.

In the processing section 12 of the memory space 2, the video data V2, V3, V4 inputted by the input selecting section 20 are selected at a predetermined timing, and the writing processing section 22 and the reading processing section 24 are selected. By controlling the writing and reading of the input video data to and from the memory 26, video data for displaying a plurality of videos is created and output to the dynamic gamma correction unit 28. The dynamic gamma correction unit 28
Correction control information calculation section 30 and gamma correction data storage section 3
2, a dynamic gamma correction process is performed on the video data input from the memory 26.

[0005] In response to a switching control signal from the multi-screen processing unit 14, the selector 16 controls the video data processed by the processing unit 10 in the memory space 1 and the video data processed by the processing unit 12 in the memory space 2. Data is output to the PDP display unit 18, and the video data V
Video P1, P2, P corresponding to 1, V2, V3, V4
3, P4 is displayed. At this time, the processing unit 10 in the memory space 1 updates the writing of the video data V1 to the memory 11, and the processing unit 12 in the memory space 2 updates the memory 26.
It is assumed that the writing of the video data V2 to the video data is updated and the writing of the video data V3 and V4 is prohibited.
As shown in FIG. 10B, video data V1, V2, V
3, video P1 (moving image), P2 (moving image) corresponding to V4,
P3 (still image) and P4 (still image) are displayed. FIG.
(A) shows a state where the video data V1 is stored in a predetermined area of the memory space 1 of the memory 11 and video data V2, V3 and V4 in different areas of the memory space 2 of the memory 26.
Are schematically displayed.

[0006]

However, in the circuit shown in FIG. 9, the dynamic gamma correction unit 28 uses the video data V2, V2 stored in each area in the memory space 2.
Since the dynamic gamma correction process is performed using video data 3 and V4 as video data stored in one area, the still images P3 and P4
The video data V3 and V4 corresponding to
2 is subjected to the dynamic gamma correction of the video data V2, and there is a problem that the brightness and the color change even though the image is a still image. That is, the dynamic gamma correction is performed as a single image including the moving image P2 as well as the still images P3 and P4.
The gamma correction values for the still images P3 and P4 change with the change in the correction control information (for example, APL (average luminance level of one screen)) calculated by the correction control information calculation unit 30, and the still image P3 that should be unchanged , The brightness and color of P4 change.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and when a gamma correction screen is displayed on a multi-image display device that displays a plurality of images including a moving image and a still image, static gamma correction is performed. It is an object of the present invention to provide a gamma correction circuit capable of preventing a change in brightness or color of an image.

[0008]

A gamma correction circuit according to the present invention writes video data of a plurality of video images including a moving image video and a still image video to different areas in a memory by a writing processing unit, and reads the video data by a reading processing unit. The video data of a plurality of videos written in the memory is read out as video data written in one memory area, and the plurality of videos are read out from the memory in a multiple video display device that displays a plurality of videos on one screen by a display unit. A correction control information calculation unit for calculating dynamic gamma correction control information based on the obtained video data;
Gamma correction data storing a plurality of sets of gamma correction data set in advance corresponding to a plurality of moving image gamma correction curves.
A corresponding set of gamma correction data is selected from the gamma correction data storage unit based on the dynamic gamma correction control information calculated by the data storage unit and the correction control information calculation unit, and read out from the memory. A dynamic gamma correction unit that performs gamma correction processing on video data, and performs gamma correction processing on the video data read from the memory using gamma correction data set in advance for still images. A static gamma correction unit, video data corrected by the dynamic gamma correction unit, and video data corrected by the static gamma correction unit based on a video display position signal designating a video display position on the display unit. Video data switching means for switching the data and outputting the data to a display unit. In such a configuration, the video data switching means converts the video data corrected by the dynamic gamma correction unit and the video data corrected by the static gamma correction unit based on the moving image video display position signal. Since the image is switched and output to the display unit, the moving image of the plurality of images displayed on the display unit is displayed with the image data corrected by the dynamic gamma correction unit, and the static gamma correction is performed for the still image image. The image based on the image data corrected by the section is displayed. For this reason, the still image displayed on the display unit is not affected by the dynamic gamma correction, and it is possible to prevent the brightness and color of the still image from being changed by the dynamic gamma correction.

When a moving image displayed on the display unit is switched to a still image, it is possible to prevent a change in brightness and color of a displayed image at the time of the switching, and to determine an optimal gamma for the switched still image. In order to perform the correction processing, a gamma correction data storage buffer for enabling rewriting of gamma correction data used in the static gamma correction unit is provided for a plurality of videos, and a moving image of the plurality of videos is provided. Gamma correction data output for outputting a set of gamma correction data selected for a moving image immediately before switching from a gamma correction data storage unit based on a display screen still control signal for switching to a still image Gamma correction data output from the gamma correction data output unit based on a display position control signal for designating display positions of a plurality of images, and storing a plurality of gamma correction data. A first switching unit for switching to and outputting a corresponding gamma correction data storage buffer among the buffers, and a static gamma correction for the gamma correction data of the corresponding gamma correction data storage buffer based on the display position control signal. A second switching unit for outputting gamma correction data to the static gamma correction unit for use in the unit.

In order to easily generate a moving image display position signal as a switching control signal to the image data switching means, a horizontal direction output from a read processing unit to a memory for designating a display area on a display unit And a moving image display position signal generating unit for generating a moving image display position signal based on the address data in the vertical direction and the setting data for specifying the moving image display area on the display unit.

In the gamma correction circuit according to the present invention, video data of a plurality of videos including moving picture video and still picture video are written to different areas in the memory by the writing processing unit, and written to the memory by the reading processing unit. An input image for displaying a plurality of images in a multi-image display device that reads out image data of a plurality of images as image data written in one memory area and displays the plurality of images on one screen by a display unit. A correction control information calculation section for calculating dynamic gamma correction control information based on the data; and gamma correction data storing a plurality of sets of gamma correction data set in advance corresponding to a plurality of moving image gamma correction curves. A set of corresponding data stored in the gamma correction data storage unit based on the dynamic gamma correction control information calculated by the correction control information calculation unit. A dynamic gamma correction unit that selects gamma correction data and performs gamma correction processing on input video data; and a video processing unit that writes video data corrected by the dynamic gamma correction unit in a memory by a writing processing unit. It is characterized in that it is video data of a plurality of videos to be written in different areas. In such a configuration, input video data for displaying a plurality of videos is subjected to gamma correction processing by a dynamic gamma correction unit and then written to different areas in the memory, and the written video data of the plurality of videos is written. The data is read out as video data written in one memory area, and a plurality of corresponding videos are displayed on the display unit. Therefore, the video data of a plurality of videos written in different areas in the memory becomes video data corrected by the dynamic gamma correction unit at the preceding stage with the optimum gamma correction data. The video data of the still image read out from the memory is always the same data, that is, the gamma correction data (corresponding to the gamma correction curve) which is optimal for the video and is fixed and processed. Therefore, the brightness and color of the still image do not change due to the dynamic gamma correction, and the brightness and color of the displayed image do not change when the moving image is switched to the still image. A circuit configuration for performing the gamma correction process can be simplified.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows a first embodiment of a gamma correction circuit according to the present invention, and the same parts as those in FIG. 9 are denoted by the same reference numerals, and detailed description is omitted. In FIG. 1, 10
Is a processing unit in the memory space 1, 12a is a processing unit in the memory space 2, 14 is a multi-screen processing unit, 16 is a selector, and 18 is a PDP display unit. Processing unit 10 of the memory space 1
Performs predetermined processing by controlling writing and reading of the input video data V1 to and from the memory 11. The processing unit 12a of the memory space 2 performs predetermined processing described later on the input video data V2, V3, and V4.
The selector 16 receives the video data V1 processed by the processing unit 10 in the memory space 1 and the memory space 2 in response to a switching control signal from the multi-screen processing unit 14.
Video data V2, V3, V4 processed by the processing unit 12 of FIG.
Are output to the PDP display unit 18 to display the images P1, P2, P3, and P4 corresponding to the image data V1, V2, V3, and V4 as shown in FIG.

The processing unit 12a of the memory space 2
Input selection unit 20, writing processing unit 22, memory 26, dynamic gamma correction unit 28, correction control information calculation unit 30, and gamma correction data storage unit 32 similar to the processing unit 12 of FIG.
And a selector 36 as a video data switching means. The input selector 20 selects the input video data V2, V3, and V4 at a predetermined timing and outputs the selected video data to the memory 26. Write processing unit 2
2 controls writing of each of the video data V2, V3 and V4 selected and input by the input selection unit 20 to different areas of the memory space of the memory 26, and the read processing unit 24a The video data V2, V3, and V4 written in the memory 26 are controlled to be read as the video data written in one memory area.

The correction control information calculating section 30 calculates correction control information (for example, APL) based on the video data read from the memory 26. The gamma correction data
The data storage unit 32 stores a plurality of sets of gamma correction data set corresponding to a plurality of moving image gamma correction curves. The dynamic gamma correction unit 28 stores a corresponding one of the gamma correction data from the gamma correction data storage unit 32 based on the correction control information calculated by the correction control information calculation unit 30.
A set of gamma correction data is selected, and gamma correction processing is performed on the video data read from the memory 26.
The static gamma correction unit 34 reads from the memory 26 using gamma correction data (gamma correction data set corresponding to a gamma correction curve for a still image) previously stored in a built-in table. Gamma correction processing is performed on the output video data. The selector 36 controls the moving image (for example, P2 corresponding to V2) on the PDP display unit 18.
The video data corrected by the dynamic gamma correction unit 28 and the video data corrected by the static gamma correction unit 34 are switched based on the moving image video display position signal designating the display position 2). Output.

The write processing unit 22 is described in detail in FIG.
, Horizontal counters 38 and 40, horizontal decoders 42 and 44, vertical counters 46 and 48, vertical decoder 5
0, 52 and AND circuits 54, 56, 58, 60.

The horizontal counter 38 counts the clock CK using the horizontal synchronizing signal Hsy1 included in the input video data (V2, V3, V4, for example, V3) as a reset signal. The horizontal decoder 42 uses the count value Q of the horizontal counter 38 to set horizontal image capture start point data HVTS and horizontal image capture end point data H as set values.
The VTE is decoded, and a signal X1 indicating an effective area during a horizontal scanning period in the input video space is output. This signal X
1 is, for example, from the start point data HVTS to the end point data HVT.
It goes to H level until E. The horizontal counter 40
The horizontal synchronization signal Hsy1 is set as the load signal LD.
The horizontal memory write start data HMWS is taken in as data, the clock CK is counted, and the count value Q is output to the memory 26 as a horizontal address H-AD. The horizontal decoder 44 uses the count value Q of the horizontal counter 40 to set horizontal memory write end point data HMWE as a set value.
And outputs a signal X2 indicating a horizontal write area in the memory space. This signal X2 is at H level, for example, from the start data HMWS to the end data HMWE.
Level. The AND circuit 54 outputs the signal X1 and the signal X
The AND signal of 2 is output to the enable terminal of the horizontal counter 40 as an enable signal EN.

The vertical counter 46 counts the clock CK using the vertical synchronizing signal Vsy1 included in the input video data (for example, V3) as a reset signal. The vertical decoder 50 uses the count value Q of the vertical counter 46 to read the vertical video capture start point data VVT as setting data.
S and the vertical video capture end point data VVTE are decoded, and a signal Y1 indicating an effective area during the vertical scanning period in the input video space is output. The signal Y1 is at H level, for example, from the start point data VVTS to the end point data VVTE. The vertical counter 48 receives the vertical memory write start data VMWS as setting data using the vertical synchronizing signal Vsy1 as the load signal LD, counts the clock CK, and sets the count value Q as the vertical address V-AD. 26. The vertical decoder 50 decodes the vertical memory write end data VMWE as setting data using the count value Q of the vertical counter 48, and outputs a signal Y2 indicating a vertical effective area in the memory space. I do. This signal Y2 is, for example, starting point data VMWS.
To the end point data VMWE. The AND circuit 56 outputs an AND signal of the signal Y1 and the signal Y2 to the enable terminal of the vertical counter 48 as an enable signal EN.

The AND circuit 58 comprises a signal X1 and a signal Y.
The AND circuit 60 outputs a logical AND signal of the output signal of the AND circuit 58 and the display screen still control signal to the enable terminal of the memory 26 as an enable signal. The display screen still control signal is a signal given as a set value, and has an H level for a moving image display area and an L level for areas other than the moving image display area (including the still image display area). For this reason, the memory 26 can write in the moving image display area for the memory space corresponding to the effective area (the area corresponding to the logical product signal of the signal X1 and the signal Y1) of the input video space, (Including the display area) is write-protected.

As shown in FIG. 3, the read processing section 24a includes horizontal counters 62 and 64, horizontal decoders 66 and 68, vertical counters 70 and 72, vertical decoders 74 and 76, an AND circuit 78, 80 and 82.

The horizontal counter 62 counts a clock CK using a horizontal synchronizing signal Hsy2 included in a scanning signal for displaying an image on the PDP display unit 18 as a reset signal RST. The horizontal decoder 66 decodes the horizontal memory read start point data HMRS and the horizontal memory read end point data HMRE as set values using the count value Q of the horizontal counter 62, and outputs a horizontal scan period in an output video space. A signal X3 indicating the middle effective area is output. The signal X3 is, for example, from the start data HMRS to the end data.
H level until HMRE. The horizontal counter 64 counts the clock CK using the signal X3 as the enable signal EN, the horizontal synchronization signal Hsy2 as the reset signal RST, and outputs the count value Q to the memory 26 as the horizontal address H-AD.

The vertical counter 70 counts the clock CK using the vertical synchronizing signal Vsy2 included in the scanning signal for displaying an image on the PDP display unit 18 as a reset signal RST. The vertical decoder 74 decodes the vertical memory read start point data VMRS and the vertical memory read end point data VMRE as set values using the count value Q of the vertical counter 70, and outputs the vertical scan period in the output video space. The signal Y1 indicating the middle effective area is applied three times. This signal Y3 is, for example, from the start point data VMRS to the end point data.
H level until the VMRE. The vertical counter 72 counts the clock CK using the signal Y3 as the enable signal EN, the vertical synchronization signal Vsy2 as the reset signal RST, and outputs the count value Q to the memory 26 as the vertical address H-AD.

The AND circuit 78 outputs an AND signal of the signal X3 and the signal Y3 to the enable terminal of the memory 26 as an enable signal EN. Therefore, the memory 26 is enabled during the effective area during the horizontal scanning period and the vertical scanning period in the output video space.

The horizontal decoder 68 uses the count value Q of the horizontal counter 64 to set horizontal memory write start data HMWS and horizontal memory write end data as set values.
HMWE, and outputs a signal X4 indicating the horizontal display position of the moving image in the output image space. This signal X4 is, for example, the starting point data H in the output video space.
It is at H level from MWS to the end point data HMWE. The vertical decoder 76 uses the count value Q of the vertical counter 72 to set vertical memory write start data VMWS and vertical memory write end data VMW as set values.
E, and outputs a signal Y4 indicating the vertical display position of the moving image in the output image space. This signal Y4
Becomes H level in the output video space from the start point data VMWS to the end point data VMWE, for example. The logical product circuit 80 outputs a logical product signal of the signal X4 and the signal Y4, and the logical product circuit 82 displays a logical product signal of the output signal of the logical product circuit 80 and a display screen still control signal in a moving image display. The moving image display position signal is output as a position signal, and controls the switching of the selector 36 in the memory space 2. The horizontal decoder 68, the vertical decoder 76, and the AND circuits 80 and 82 constitute a moving picture image display position signal generating section 84.

Next, the operation of FIGS. 1 to 3 will be described with reference to FIGS.
Will be described together. First, (A) describes the overall operation mainly in FIG. 1, then (B) describes the operation of writing to the memory 26 mainly in FIG. 2, and then (C) illustrates the memory operation mainly in FIG. 3. The operation of the readout process from 26 will be described.

(A) Overall operation (1) The input video data V1 is stored in the memory space 1 of the memory 11 as shown on the left side of FIG. The data is written at a predetermined timing, and then the video data V1 is read from the memory 11 at a predetermined timing, so that a predetermined process is performed on the memory space 1 and one of the selectors 16 is used as the video data V1 for display. Input to the input side.

(2) A plurality of input video data V2, V
3 and V4 are selected at a predetermined timing in the input selection section 20 of the processing section 12a in the memory space 2. The selected video data V2, V3 and V4 are written in the writing processing section 22.
As shown on the right side of FIG.
Is written to three different memory areas in the memory space 2 of the memory. The video data V2, V written in the memory 26
3 and V4 are stored in the memory space 2 by the read processing unit 24a.
Is read from the memory 26 as one memory area,
The read video data V2, V3, and V4 are input to the dynamic gamma correction unit 28, the correction control information calculation unit 30, and the static gamma correction unit 34.

(3) The correction control information calculation section 30 calculates dynamic gamma correction control information (for example, APL (average luminance level)) for each of the video data V2, V3, and V4. In the dynamic gamma correction section 28, based on the dynamic gamma correction control information calculated by the correction control information calculation section 30, a plurality of sets of gamma correction data stored in the gamma correction data storage section 32 in advance. Is selected as a set of gamma correction data.
A gamma correction process is performed on the video data V2, V3, and V4 read from the. Static gamma correction unit 34
Then, gamma correction processing is performed on the video data V2, V3, and V4 read from the memory 26 using gamma correction data for a still image stored in advance in a built-in table.

(4) The selector 36 controls the read processing unit 24
The video data corrected by the dynamic gamma correction unit 28 and the video data corrected by the static gamma correction unit 34 based on the video display position signal generated by the video display position signal generation unit 84 in FIG. And the selector 16 as video data V2, V3, and V4 for display.
Is output to the other input side. For example, the selector 36
When the moving image display position signal is at the H level, the connection is controlled to a solid line, and when the moving image display position signal is at the L level, the connection is controlled to a dotted line. At this time, since the video data V2 is video data for moving images and the video data V3 and V4 are video data for still images, the video data corrected by the dynamic gamma correction unit 28 is used. V2 and the video data V3 and V4 corrected by the static gamma correction unit 34 are selected by the selector 36 and output to the other input side of the selector 16.

(5) In response to a switching control signal from the multi-screen processing unit 14, the selector 16 controls the video data V1 input to one input side and the video data V2 and V3 input to the other input side. , And V4 are switched at a predetermined timing and output to the PDP display unit 18. As shown in FIG. 10B, the PDP display unit 18 supports video data V1, V2, V3, and V4. Video P1 (moving image),
P2 (moving image), P3 (still image), and P4 (still image) are displayed at predetermined display positions. At this time, P2 of the moving image corresponds to the video data V2 corrected by the dynamic gamma correction unit 28, and P3 and P4 of the still image correspond to the video data V3 and V4 corrected by the static gamma correction unit 34. Therefore, it is possible to prevent the brightness and color of still images P3 and P4 from being changed by the gamma correction of the dynamic gamma correction unit 28.

(B) Write Processing Operation (1) In FIG. 2, the horizontal counter 38 counts the clock CK using the horizontal synchronization signal Hsy1 as a reset signal.
The horizontal decoder 42 decodes the horizontal video capture start point data HVTS and horizontal video capture end point data HVTE using the count value Q of the horizontal counter 38, and outputs a signal X1.
This signal X1 is a signal from the start data HVTS to the end data H.
It is at H level until VTE, and indicates an effective area in the horizontal scanning period in the input video space. For example, as for the input video data V2, the signal X1 indicates an effective area in the horizontal scanning period in the input video space as shown in FIG.

(2) The vertical counter 46 detects the vertical synchronizing signal V
The clock CK is counted using sy1 as a reset signal, the vertical decoder 50 decodes the vertical video capture start point data VVTS and the vertical video capture end point data VVTE using the count value Q of the vertical counter 46, and outputs a signal Y1. Is output. This signal Y1 is output from the start point data VVT to the end point data VVT.
It is at the H level until E, indicating an effective area in the vertical scanning period in the input video space. For example, as for the input video data V2, the signal Y1 indicates an effective area in the vertical scanning period in the input video space as shown in FIG.

(3) The signal X1 and the signal Y1 are ANDed by the AND circuit 5.
8, the AND circuit 58 outputs a logical product signal of the signal X1 and the signal Y1, and the logical product circuit 60 enables the logical product signal of the output signal of the logical product circuit 58 and the display screen still control signal. To the enable terminal of the memory 26. This display screen still control signal is a signal given as a set value, and is at the H level in the moving image display area, and is other than the moving image display area (including the still image display area).
Is at L level, the memory 26 can write in the moving image display area for the memory space corresponding to the effective area of the input video space (the area corresponding to the logical product signal of the signal X1 and the signal Y1). Writing is prohibited in areas other than the area (including the still image display area). For example, as for the input video data V2, since the display screen still control signal remains at the H level, writing to the corresponding area (V2) in the memory space is updated, and the input video data V2 is updated.
Is a moving image. Also, input video data
As for the data V3 and V4, after the display screen still control signal goes low, writing to the corresponding areas (V3 and V4) of the memory space shown in FIG. 4B is prohibited, and the input video data V3 , V4 corresponding to the still images.

(4) The horizontal counter 40 takes in the horizontal memory write start data HMWS using the horizontal synchronization signal Hsy1 as the load signal LD, counts the clock CK, and counts the count value Q as the horizontal address H-AD to the memory 26. Output. The horizontal decoder 44 decodes the horizontal memory write end point data HMWE using the count value Q of the horizontal counter 40, and outputs a signal X2. This signal X2 is at the H level from the start data HMWS to the end data HMWE, and indicates a horizontal writing area in the memory space. For example, as for the input video data V2, the signal X2 indicates a horizontal writing area in the memory space as shown in FIG. AND circuit 54
Is the logical product of the signal X1 and the signal X2 and the enable signal E
It outputs to the enable terminal of the horizontal counter 40 as N. Therefore, the horizontal address H-AD to the memory 26 is
Is an address corresponding to the horizontal writing area (the area indicated by the signal X2) in the memory space shown in FIG. 4B.

(5) The vertical counter 48 receives the vertical memory write start data VMWS using the vertical synchronization signal Vsy1 as the load signal LD, counts the clock CK, and counts the count value Q as the vertical address V-AD to the memory 26. Output. The vertical decoder 50 decodes the vertical memory write end data VMWE using the count value Q of the vertical counter 48, and outputs a signal Y2. This signal Y2 is at H level from the start point data VMWS to the end point data VMWE, and indicates a vertical effective area in the memory space. For example, as for the input video data V2, the signal Y2 indicates a vertical writing area in the memory space as shown in FIG. 4B. The AND circuit 56 outputs the AND signal of the signal Y1 and the signal Y2 to the enable signal EN.
To the enable terminal of the vertical counter 48.
Therefore, the vertical address V-AD to the memory 26 is an address corresponding to the vertical writing area (the area indicated by the signal Y2) in the memory space shown in FIG. 4B.

(C) Read Processing Operation (1) The horizontal counter 62 shown in FIG.
The horizontal decoder 66 decodes the horizontal memory read start data HMRS and the horizontal memory read end data HMRE using the count value Q of the horizontal counter 62 to generate a signal X3. Output. The signal X3 is at the H level from the start data HMRS to the end data HMRE, and indicates an effective area in the output video space during the horizontal scanning period. This signal X3 is, for example, as shown in FIG.
As shown in (c), the effective area during the horizontal scanning period in the output video space is shown.

(2) The vertical counter 70 outputs the vertical synchronizing signal V
The clock CK is counted using sy2 as a reset signal RST, the vertical decoder 74 decodes the vertical memory read start data VMRS and the vertical memory read end data VMRE using the count value Q of the vertical counter 70, and outputs the signal Y3. Output. This signal Y3 is at the H level from the start data VMRS to the end data VMRE, and indicates an effective area in the output video space during the vertical scanning period. The signal Y3 indicates, for example, an effective area in the output image space during the vertical scanning period as shown in FIG. 4C for the image data V2.

(3) The signal X3 and the signal Y3 are ANDed by the AND circuit 7.
8, the AND circuit 78 uses the AND signal of the signal X3 and the signal Y3 from the AND circuit 78 as an enable signal.
Output to the enable terminal. For this reason, it corresponds to the effective area (the H level area of the signal X3) and the effective area (the H level area of the signal Y3) during the horizontal scanning period in the output video space shown in FIG. 4C. period,
The memory 26 is in a readable period.

(4) The horizontal counter 64 counts the clock CK using the signal X3 as the enable signal EN, the horizontal synchronization signal Hsy2 as the reset signal RST, and outputs the count value Q to the memory 26 as the horizontal address H-AD. Therefore, the horizontal address H-AD to the memory 26 is
The address corresponds to the horizontal direction area (the area indicated by the signal X3) in the output video space shown in (c). The vertical counter 72 sets the signal Y3 as the enable signal EN,
The clock CK is counted using the vertical synchronization signal Vsy2 as a reset signal RST, and the count value Q is output to the memory 26 as a vertical address H-AD. Therefore, the memory 26
The vertical address V-AD to the address becomes an address corresponding to a vertical direction area (an area indicated by the signal Y3) in the output video space shown in FIG. 4C.

(5) Moving picture image display position signal generator 84
Operates as follows to generate a moving image video display position signal.

(5-1) The horizontal decoder 68 decodes the horizontal memory write start data HMWS and the horizontal memory write end data HMWE using the count value Q of the horizontal counter 64, and outputs a signal X4. This signal X4 is at H level from the start data HMWS to the end data HMWE, and indicates the horizontal display position of the video in the output video space. The signal X4 is, for example, a signal as shown in FIG. 4C for the video data V2.

(5-2) The vertical decoder 76 uses the count value Q of the vertical counter 72 to read the vertical memory write start point.
The data VMWS and the vertical memory write end data VMWE are decoded, and a signal Y4 is output. The signal Y4 is at H level from the start data VMWS to the end data VMWE, and indicates the vertical display position of the video in the output video space. The signal Y4 is, for example, a signal as shown in FIG. 4C for the video data V2.

(5-3) The logical product circuit 80 outputs a logical product signal of the signal X4 and the signal Y4, and the logical product circuit 82 converts the logical product signal of the output signal of the logical product circuit 80 and the display screen still control signal into a moving image. It is output as a video display position signal. For this reason,
The video display position signal is a video data V corresponding to the video.
2 is high when the AND signal of the signal X4 and the signal Y4 is at the H level because the display screen still control signal is at the H level.
Video data V3, V corresponding to still images
For No. 4, since the display screen still control signal is at L level, even when the logical product signal of the signal X4 and the signal Y4 is at H level, it is at L level. The moving image display position signal controls the switching of the selector 36 in the memory space 2 in FIG. 1, so that the video data V2 subjected to the gamma correction processing by the dynamic gamma correction unit 28 and the gamma correction by the static gamma correction unit 34 The corrected video data V3 and V4 are output to the PDP display unit 18 via the selectors 36 and 16, and P2 (moving image), P3 (still image), and P4 ( (Still image) is displayed.

FIG. 5 shows a second gamma correction circuit according to the present invention.
1 shows an embodiment, and the same parts as those in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted. The gamma correction circuit of FIG.
In addition to having the features of the gamma correction circuit in FIG. 1, when switching a part or all of a plurality of images from a moving image to a still image, it prevents the brightness and color of the displayed image from changing, and The gamma correction is optimized for a still image. In FIG. 5, 8
6 is a correction data output unit, 88 and 90 are first and second switching units, 921, 922 and 923 are gamma correction data storage buffers, and 34a is a static gamma correction unit.

The correction data output section 86 is a set selected for the moving image immediately before switching from the gamma correction data storage section 32 based on a display screen still control signal for switching a moving image to a still image. Output gamma correction data. The first switching unit 88 stores the gamma correction data output from the correction data output unit 86 based on a display position control signal that specifies the display position of each image in the gamma correction data storage buffer. The output is switched to the corresponding gamma correction data storage buffer among 921, 922, and 923.

The second switching section 90 controls the gamma correction data storage buffer 92 based on the display position control signal.
The gamma correction data of the corresponding gamma correction data storage buffer among 1, 922 and 923 is switched and output to the static gamma correction unit 34a. The display position control signal is, as shown in FIG.
1, S2, S3 (for example, the H level) are
4 for encoding. This signal S
Reference numerals 1, S2, and S3 denote signals for specifying display positions on the PDP display unit 18 of the images P1, P2, and P3 corresponding to the image data V1, V2, and V3, for example, as shown in FIGS. ) Is a signal for specifying the display position of each of the images P1, P2, and P3.

The static gamma correction unit 34a includes:
The video data read from the memory 26 is stored in the second
The switching section 90 performs gamma correction processing using gamma correction data that is switched and output from each of the gamma correction data storage buffers 921, 922, and 923.

Next, the operation of FIGS. 5 and 6 will be described with reference to FIG. (1) The input video data V1, V2, and V3 are selected at a predetermined timing in the input selection unit 20, and the selected video data V1, V2, and V3 are written in the writing processing unit 22.
The video data V1, V2, and V3 are read from the memory 26 by using the memory space as one memory area by the read processing unit 24a. The process until the input video data V1, V2, and V3 are input to the dynamic gamma correction unit 28, the correction control information calculation unit 30, and the static gamma correction unit 34a is the same as that in FIG.

(2) The correction control information calculation section 30 calculates dynamic gamma correction control information for each of the video data V1, V2 and V3. In the dynamic gamma correction section 28, based on the dynamic gamma correction control information calculated by the correction control information calculation section 30, a plurality of sets of gamma correction data stored in the gamma correction data storage section in advance. One set of gamma correction data is selected, and the video data V1, V read from the memory 26 is selected.
2. Gamma correction for V3 is performed.

(3) Gamma correction data storage buffer 92
The gamma correction data stored in advance as the initial values in each of 1, 922, and 923 is switched by the second switching unit 90 and output to the static gamma correction unit 34a. The gamma correction data stored in the gamma correction data storage buffers 921, 922, and 923 is used to store the gamma correction data in the memory 2.
The gamma correction process is performed on the video data V1, V2, and V3 read out from the step S6.

(4) The selector 36 selects the read processing unit 24
5A, the video data corrected by the dynamic gamma correction unit 28 and the video data corrected by the static gamma correction unit 34a based on the video display position signal generated by the video display position signal generation unit 84. And switch to P
Output to DP display unit 18. At this time, the video data V1 and V2 corresponding to the video P1 and P2 shown in FIG. 7A are video data for a moving image and the video data V3 corresponding to the video P3.
Are video data for still images, the video data V1 and V2 corrected by the dynamic gamma correction unit 28.
And the video data V3 corrected by the static gamma correction unit 34 are selected by the selector 36 and output to the PDP display unit 18. At this time, as shown in FIG. 7A, images P1 (moving image), P2 (moving image), and P3 (still image) corresponding to the image data V1, V2, V3 are displayed on the PDP display unit 18. However, P1 and P2 of the moving image correspond to the video data V2 corrected by the dynamic gamma correction unit 28, and P3 of the still image corresponds to the video data V3 corrected by the static gamma correction unit 34a. Therefore, it is possible to prevent the brightness and color of the still image P3 from changing due to the gamma correction of the dynamic gamma correction unit 28.

(5) Next, as shown in FIGS. 7 (a) and 7 (b), the operation when P2 of the display images P1, P2 and P3 of the PDP display unit 18 is switched from a moving image to a still image. explain.

(5-1) When a display screen still control signal for switching a moving image to a still image is input to the correction data output unit 86, the dynamic gamma correction unit 28 switches the correction data output unit 86. A set of gamma correction data selected for the previous moving picture P2 is output from the gamma correction data storage unit 32.

(5-2) The first switching unit 88 switches the display positions of the images P1, P2, and P3 based on the display position control signal, so that the moving image P2 is read from the gamma correction data storage unit 32. The selected gamma correction data is stored in the gamma correction data storage buffer 9 for the corresponding video among the gamma correction data storage buffers 921, 922, and 923.
22 and the contents are rewritten.

(5-3) The second switching section 90 switches the display positions of the images P1, P2, and P3 based on the display position control signal, so that the gamma correction data storage buffers 921, 922, and 923 are provided. The gamma correction data stored in each of them is switched by the second switching unit 90 and output to the static gamma correction unit 34a. At this time, the gamma correction data in the gamma correction data storage buffer 922 becomes the rewritten gamma correction data.

(5-4) For the still picture P2 shown in FIG. 7 (b), the gamma correction data does not change when the picture is switched from the moving picture to the still picture. It can prevent the pod color from changing,
Optimal gamma correction can be performed. For example, gamma correction data written as an initial value in the gamma correction data storage buffer 922 corresponds to a gamma correction curve 5 (for example, a gamma correction curve at the center of the gamma correction curves 1 to 9). If the gamma correction data rewritten based on the switching of the moving image to the still image is the gamma correction curve 2, the switched still image P2 as shown in FIG. The most suitable gamma correction curve is gamma correction curve 2. Further, since the gamma correction data does not change when the moving image is switched to the still image, it is possible to prevent the brightness and color of the image P2 from changing at the time of this switching.

FIG. 8 shows a third embodiment of the gamma correction circuit according to the present invention.
5 shows an embodiment, and the same parts as those in FIGS. 5 and 9 are denoted by the same reference numerals, and detailed description thereof will be omitted. The gamma correction circuit of FIG. 8 is characterized in that the features of the gamma correction circuit of FIG. 5 are achieved with a simple circuit configuration by providing a dynamic gamma correction unit 28 in a stage preceding the memory 26. . That is, in the gamma correction circuit of FIG. 5, the selector 36, the static gamma correction unit 34a,
Correction data output unit 86, first and second switching units 88 and 90, and gamma correction data storage buffers 921, 922 and 92.
3 can be omitted and the selector 3
6, a display screen still control signal to the correction data output unit 86, and first and second switching units 88 and 9.
The display position control signal to 0 can be omitted.

In FIG. 8, reference numeral 20 denotes input video data V
An input selection unit for selecting and outputting 1, V2, and V3 at a predetermined timing. A dynamic gamma correction unit 28 and a correction control information calculation unit 30 are connected to the output side of the input selection unit 20, and the dynamic gamma correction is performed. A memory 26 and a PDP display unit 18 are sequentially connected to an output side of the unit 28. The gamma correction data storage unit 32 is connected to the dynamic gamma correction unit 28, and the write processing unit 22 and the read processing unit 24 are connected to the memory 26.

Next, the operation of FIG. 8 will be described with reference to FIG. (1) The input video data V1, V2, and V3 are selected at a predetermined timing in the input selection unit 20, and the selected video data V1, V2, and V3 are selected by the correction control information calculation unit 30 and the dynamic gamma. Input to the correction unit 28.

(2) The correction control information calculation section 30 calculates dynamic gamma correction control information for each of the video data V1, V2, and V3. In the dynamic gamma correction section 28, based on the dynamic gamma correction control information calculated by the correction control information calculation section 30, a plurality of sets of gamma correction data stored in the gamma correction data storage section in advance. One set of gamma correction data is selected, and the video data V1 and V selected by the input selection unit 20 are selected.
2. Gamma correction for V3 is performed. Therefore, optimal gamma correction is performed for each of the video data V1, V2, and V3.

(3) The video data V1, V2 and V3 gamma-corrected by the dynamic gamma correction unit 28 are stored in the memory 2
Enter 6 In this memory 26, the input video data V
1, V2, and V3 are written into three different memory areas of the memory space by the write processing unit 22, and the video data V1, V2, and V3 are read from the memory 26 by the read processing unit 24 using the memory space as one memory area. Are read out, and the read out video data V1, V2, V3 are output to the PDP display unit 18. At this time, video data V1 and V
2. Of V3, the video corresponding to the video data which is updated without being prohibited from being written is displayed as a moving image, and the video corresponding to the video data which is prohibited and is not updated is displayed as a still image. Is done. For example, video data V1, V2,
If the writing of the video data V3 of the video data V3 is prohibited and is not updated, the video data P1, P2, and P3 corresponding to the video data V1, V2, and V3 are displayed as moving images as shown in FIG. , Moving images, still images, and video data V1,
When writing of the video data V2 and V3 of V2 and V3 is prohibited and is not updated, the corresponding video P1,
P2 and P3 are displayed as a moving image, a still image, and a still image as shown in FIG.

[0061]

The gamma correction circuit according to the present invention includes a correction control information calculation section, a gamma correction data storage section, a dynamic gamma correction section, a static gamma correction section, and a video data switching means in a multiple video display apparatus. The video data switching means switches between the video data corrected by the dynamic gamma correction unit and the video data corrected by the static gamma correction unit based on the moving image video display position signal, and displays the video data. Of the plurality of images displayed on the display unit, an image based on the image data corrected by the dynamic gamma correction unit is displayed for a moving image, and a static gamma correction unit is corrected for a still image image. It is configured so that an image based on the image data is displayed. For this reason, the still image displayed on the display unit is not affected by the dynamic gamma correction, and it is possible to prevent the brightness and color of the still image from being changed by the dynamic gamma correction.

A plurality of gamma correction data storage buffers for storing still image gamma correction data for each of a plurality of images, and a display screen still control signal for switching a moving image among the plurality of images to a still image. A gamma correction data output unit for outputting a set of gamma correction data selected for a moving image immediately before switching from the gamma correction data storage unit based on the gamma correction data storage unit, and a display position of each image of a plurality of images. The gamma correction data output from the gamma correction data output unit is switched to a corresponding gamma correction data storage buffer among a plurality of gamma correction data storage buffers based on a designated display position control signal. A gamma correction data storage buffer for a corresponding gamma correction data storage buffer among a plurality of gamma correction data storage buffers based on a first switching unit for outputting and a display position control signal. A second switching unit for outputting data, and a static gamma correction unit for performing gamma correction processing on video data read from the memory using the gamma correction data output from the second switching unit. In this case, when the moving image displayed on the display unit is switched to a still image, it is possible to prevent a change in the brightness and color of the displayed image at the time of the switching, and to prevent a change in the still image after the switching. Optimal gamma correction processing can be performed.

The horizontal and vertical address data output from the read processing unit to the memory for designating the effective display area on the display unit, and the setting data for designating the moving picture image display area on the display unit. In the case where a moving image display position signal generating section for generating a moving image display position signal based on the above is provided, a moving image display position signal as a switching control signal to be transmitted to the image data switching means is easily generated. be able to.

The gamma correction circuit according to the present invention comprises a correction control information calculation section and a gamma correction data
A data storage unit and a dynamic gamma correction unit, wherein the video data corrected by the dynamic gamma correction unit is used as video data of a plurality of videos to be written to different areas in the memory by the writing processing unit. The input video data for displaying the video data is subjected to gamma correction processing by the dynamic gamma correction unit, and then written to different areas in the memory, and the written video data of a plurality of video data is written to one memory area. Since a plurality of images are read out as data and the corresponding plurality of images are displayed on the display unit, the image data of the plurality of images written in different areas in the memory are optimized by the dynamic gamma correction unit in the preceding stage. Video data corrected by the gamma correction data. For this reason, the video data of the still image read from the memory is always the same video data, and the gamma correction data is optimal for the video and is fixed and processed.
Become Therefore, the brightness and color of the still image do not change due to the dynamic gamma correction, and even when the moving image is switched to the still image, the brightness and color of the displayed image do not change at the time of this switching. It is possible to simplify the circuit configuration for performing the optimal gamma correction processing on the subsequent still image.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a first embodiment of a gamma correction circuit of a multi-image display device according to the present invention.

FIG. 2 is a block diagram showing a specific example of a write processing unit 22 in FIG.

FIG. 3 is a block diagram illustrating a specific example of a read processing unit 24a in FIG. 1;

FIG. 4 is a diagram showing a video data stored in a memory 26 in FIGS. 1 to 3;
FIG. 4 is an explanatory diagram showing writing and reading of data by an image.

FIG. 5 is a block diagram showing a second embodiment of the gamma correction circuit of the multi-image display device according to the present invention.

6 is a block diagram of a circuit that generates a display position control signal in FIG.

7A and 7B show display examples of the PDP display unit 18 in FIG. 5, wherein FIG. 7A shows a display example before switching the moving image P2 to the still image P2, and FIG. FIG. 10 is a diagram showing a display example after switching to.

FIG. 8 is a block diagram showing a third embodiment of the gamma correction circuit of the multi-image display device according to the present invention.

FIG. 9 is a block diagram showing a conventional example.

FIG. 10 shows a relationship between a memory space and a display image.
(A) is a memory space 2 of the two memory spaces 1 and 2
Of three video data V2, V3,
FIG. 5B shows a state in which V4 is written, and FIG.
As one memory area, video data V2, V3, V4
And the video data V read from the memory space 1
FIG. 6 is a diagram showing a state displayed on the display unit together with the number 1.

[Explanation of symbols]

10 ... Processing unit of memory space 1 11 ... Memory 12
a: processing unit in the memory space 2, 14: multi-screen processing unit, 16: selector, 18: PDP display unit (an example of a display unit), 20: input selection unit, 22: writing processing unit, 24, 24a: reading process Part, 26 ... memory,
28: dynamic gamma correction unit; 30: correction control information calculation unit; 32: gamma correction data storage unit;
4, 34a: Static gamma correction unit, 36: Selector (an example of video data switching means), 38, 40, 6
2, 64 ... horizontal counter, 42, 44, 66, 68 ...
Horizontal decoder, 46, 48, 70, 72 ... vertical counter, 50, 52, 74, 76 ... vertical decoder, 5
4, 56, 58, 60, 78, 80, 82: AND circuit, 84: Moving picture image display position signal generation unit, 86: Correction data output unit, 88: First switching unit, 90: Second switching unit 921 to 923: Gamma correction data storage buffer, HMRE: Horizontal memory read end data, HM
RS: Horizontal memory read start data, HMWE: Horizontal memory write end data, HMWS: Horizontal memory write start data, HVTE: Horizontal video capture end data,
HVTS: Horizontal video capture start point data, P1, P2,
P3, P4: video, V1, V2, V3, V4: video data, VMRE: vertical memory read end data, V
MRS: Vertical memory read start point data, VMWE: Vertical memory write end point data, VMWS: Vertical memory write start point data, VVTE: Vertical video capture end point data
Data, VVTS: Vertical video capture start point data.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) G09G 5/36 510 G09G 5/36 510M (72) Inventor Junichi Onodera 1116 Suenaga, Takatsu-ku, Kawasaki-shi, Kanagawa Stock Fujitsu General Limited (72) Inventor Masayuki Kobayashi 1116, Suenaga, Takatsu-ku, Kawasaki, Kanagawa Prefecture Stock Company Fujitsu General Co., Ltd. ) 5C021 PA62 PA63 PA72 PA78 PA82 PA87 PA89 RB06 SA02 SA03 SA06 XA34 YC04 ZA03 5C080 AA05 AA10 BB05 CC03 DD05 EE19 EE29 EE30 FF09 GG02 GG08 GG09 JJ01 JJ02 JJ04 JJ04 5C082 AA01 BAA31 BAA31BAA BA31BAA DA31

Claims (4)

[Claims] 1. A video processing unit which writes video data of a plurality of videos including a moving video video and a still video video to different areas in a memory by a writing processing unit, and writes the video data of a plurality of videos written in the memory by a reading processing unit. In a multiple video display device for reading data as video data written in one memory area and displaying a plurality of videos on a single screen by a display unit, a dynamic image based on the video data read from the memory. A correction control information calculation unit for calculating gamma correction control information; a gamma correction data storage unit storing a plurality of sets of gamma correction data set in advance corresponding to a plurality of moving image gamma correction curves; A corresponding set of gamma correction data is selected from the gamma correction data storage unit based on the dynamic gamma correction control information calculated by the correction control information calculation unit. A dynamic gamma correction unit for performing gamma correction processing on video data read from the memory; and a gamma correction data previously set for a still image on the video data read from the memory. A static gamma correction unit for performing a gamma correction process using data, video data corrected by the dynamic gamma correction unit based on a moving image display position signal designating a moving image display position on the display unit, and A gamma correction circuit comprising: video data switching means for switching between the video data corrected by the static gamma correction unit and outputting to the display unit. 2. A video processing unit which writes video data of a plurality of videos including a moving video video and a still video to different areas in a memory by a writing processing unit, and a video data of the plurality of videos written to the memory by a reading processing unit. In a multiple video display device for reading data as video data written in one memory area and displaying a plurality of videos on a single screen by a display unit, a dynamic image based on the video data read from the memory. A correction control information calculation unit for calculating gamma correction control information; a gamma correction data storage unit storing a plurality of sets of gamma correction data set in advance corresponding to a plurality of moving image gamma correction curves; A corresponding set of gamma correction data is selected from the gamma correction data storage unit based on the dynamic gamma correction control information calculated by the correction control information calculation unit. A dynamic gamma correction unit for performing gamma correction processing on video data read from the memory; and a plurality of gamma correction data for storing still image gamma correction data for each of the plurality of videos. A set of gamma correction selected for the moving image immediately before switching from the gamma correction data storage unit based on a storage buffer and a display screen still control signal for switching a moving image of the plurality of images to a still image. A gamma correction data output unit for outputting data; and a gamma correction data output from the gamma correction data output unit based on a display position control signal for specifying a display position of the plurality of images. A first switching section for switching to a corresponding gamma correction data storage buffer among a plurality of gamma correction data storage buffers and outputting the same, based on the display position control signal; A second switch for outputting gamma correction data of a corresponding gamma correction data storage buffer among the plurality of gamma correction data storage buffers; and a gamma correction data output from the second switch. A static gamma correction unit for performing a gamma correction process on video data read from the memory using a video data, and a video video display position signal that specifies a video video display position on the display unit. Video data switching means for switching between video data corrected by the dynamic gamma correction unit and video data corrected by the static gamma correction unit and outputting the video data to the display unit. Characteristic gamma correction circuit. 3. A horizontal and vertical address data output from a read processing unit to a memory for designating a display area on a display unit, and setting data for designating a moving picture image display area on the display unit. The gamma correction circuit according to claim 1 or 2, further comprising a moving image display position signal generating unit that generates a moving image display position signal based on the data. 4. A video processing unit which writes video data of a plurality of videos including a moving video video and a still video to different areas in a memory, and a video processing unit which writes video data of a plurality of videos written in said memory by a read processing unit. In a multiple video display device that reads data as video data written in one memory area and displays a plurality of videos on one screen by a display unit, a dynamic gamma based on input video data for displaying a plurality of videos is provided. A correction control information calculating section for calculating correction control information; a gamma correction data storage section storing a plurality of sets of gamma correction data set in advance corresponding to a plurality of moving image gamma correction curves; Based on the dynamic gamma correction control information calculated by the control information calculation unit, a set of gamma correction data corresponding from the gamma correction data storage unit.
A dynamic gamma correction unit for selecting the input video data and performing gamma correction processing on the input video data, and the video data corrected by the dynamic gamma correction unit is stored in the memory by the writing processing unit. A gamma correction circuit, wherein video data of a plurality of videos to be written in different areas is provided.