JPS61121677A - High quality television receiver - Google Patents

Abstract

PURPOSE:To expand and project an area of part of the picture by installing a buffer memory to have a capacity for at least one field at the front step of a TCI (Time, Compressed Integration) decoder and a control circuit to control to read the area of part of the memory at a low speed at the time of writing, and supplying the video signal from the above-mentioned memory to the above- mentioned decoder. CONSTITUTION:A zoom up circuit 12 is composed of a buffer memory 13 to have a capacity for one field of the video data outputted from a mixer circuit 8, an address control circuit 14 to designate respective writing and reading addresses of the memory and a zoom area setting circuit 15 where the zoom area is designated by a joy stick 15a and an action of an address control circuit 14 is changed over inside and outside the area. A static area interpolating circuit 6 obtains video data for four fields outputted from two field memories 3 and 4, and interpolates a static area part, and a dynamic area interpolating circuit 7 obtains the video data for one said field during the receiving and interpolates the dynamic area part.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Field of Application The present invention is directed to high-definition TCI (Time Television) receivers, in which color signals are time-base compressed and time-division multiplexed with luminance signals. Compressed Int.
The present invention relates to a TV receiver intended for high-definition TV signals of the type (egration).

(b) Conventional technology One of the high-definition TV systems mentioned above is the MUSE method proposed by NHK, and this method is described, for example, in the magazine ``Nikkei Electronics March 12, 1984,'' Nos. 112-116. As stated on the page, high-resolution color images at 30 frames/second are realized with 1125 scanning lines/frame. Therefore,
With this method, even if the color image is enlarged and displayed, it is possible to provide a sufficiently satisfactory image quality.

(c) Problems to be Solved by the Invention Therefore, an object of the present invention is to realize a high-quality TV receiver capable of enlarging and displaying a partial area of an image with a configuration as small as possible.

(d) Means for solving the problem A TCI that decodes TCI-type high-definition video signals.
A buffer memory having a capacity for at least one field is provided in the front stage of the dehooder, and a control circuit is provided for controlling a part of the memory to be read out at a slower speed than when loading data,
A video signal from the memory is supplied to the decoder.

(E) Use According to the above configuration, it is possible to supply a type of TCI signal in which a predetermined area of an image is enlarged from the buffer memory to the decoder, and therefore, by directly decoding this TCI signal, a color image can be enlarged.゛Can be displayed large.

(f) Embodiment Figure 1 shows the schematic configuration of the main parts of an embodiment of a high-quality TV receiver according to the present invention.
This is the basic component of an E-scheme TV receiver, and includes each of the functional blocks (1) to (11) shown in the diagram, but since this part has been explained in the previous magazine, etc., it will not be described in detail here. Explanation will be omitted.

In this embodiment, in such a known high-definition TV receiver, a mixer circuit (8) capable of deriving TCI format video data after various corrections and interpolations, and the video data C
The present invention is characterized in that a zoom-up circuit (12) is arranged between the TCI decoder circuit (9) that decodes the TCI decoder (TCI) and converts it into a normal analog three-color video signal. That is, this zoom up circuit (12) includes a buffer memory (13) having a capacity for one field of video data output from the mixer circuit ('8), and an address control for specifying each write and read address of this memory. A zoom area setting circuit (14) that allows a zoom area to be specified using a joystick (15g) and switches the operation of the address control circuit (14) inside and outside that area.
15).

Note that the static area interpolation circuit (6) and the moving area interpolation circuit (7) in FIG. The latter (7) obtains the video data for 4 fields output from the 2-field memory (3) and (4) and interpolates the still area part, and the latter (7) obtains the video data for the 1 field being received and interpolates it for the moving area. The motion detection circuit (5) detects the motion of each pixel by comparing the received video data for one field with the video data four fields before. The mixing ratio of the output signals of the two interpolation ports (6) and (7) in the mixer circuit (8) is controlled according to the output.

FIG. 2 shows the internal configuration of the zoom area setting circuit (15). That is, this circuit (15) includes an A/D conversion circuit (17) into which signals indicating the X (horizontal direction) and 2 (vertical direction) coordinate positions output from the joystick (15a) are input, and each output data thereof. counters (18), (19), and (20) that are loaded, and a color (21) that is preset with data indicating the zoom width in the x and z directions.
(22), (23), flip-flops (24), (25), and (26) that are set (S) and reset (R) by the output of each of these counters, and one more flip-flop (30), and It is provided with an OR gate (27) (28) and an AND gate (29) into which each output is input. The A/D conversion circuit <17> converts the corresponding binary data (Z
), but in response to an analog input indicating the X position, the corresponding data (X) and data four times the value (4x) are output. The reason for this will be explained later. do.

Further, FIG. 3 shows the internal configuration of the address control circuit (14) of FIG. 1. That is, this control circuit (14)
1st to 3rd H (horizontal) counters (31), (32), and (33) whose count inputs are clock pulses (CLK) bit-synchronized with the video data from the mixer circuit (8) in FIG.
), and the first one with the horizontal synchronization pulse (H) as the count input.
~4th V (vertical) counter (34) (35) (36) (
37), and first to third multiplexers (38) < 39) (40) that switch and derive the output of each counter. To explain in more detail, the first H, V
71 (31) (34) are the buffer memory (1
3) and (7) are for specifying a write address, and the second H, V counters (32) and (35) are for specifying a read address of the memory (13) in the case of normal display. Furthermore, the 3rd H
counter (33) and third 4th v counter (36) (37
) is used for specifying a read address in the case of zoom display, and one output of the third and fourth counters (36) and (37) is selected and derived by the third multiplexer (40).

the first and second H counters (31) (32) and the first and second H counters (31) and (32);
Data Xo and Zo corresponding to the initial address of the memory <13) are loaded into the V counters (34) and (35) at the timing of the horizontal synchronizing pulse (R5) and the vertical synchronizing pulse (VS), respectively. Moreover, the second H counter (
32> output is the horizontal load pulse (LH2
), the 3rd H counter (33) is fully loaded, and the output of the 2nd V counter (35) becomes low at the timing of the mW load pulse (LV2) from Figure 2.
t6. So L, Te No. 2 H, V Can'7 I (32)
(35), the output of the third H counter (33), and the output of the third multiplexer (40) are selected and derived by the second multiplexer (39). This third multiplexer (39) is switched by the control signal (CT2) from FIG.

Further, the outputs of the first H, V counters (31, 34, 7) and the second multiplexer (39) are switched and derived by the first multiplexer (38). At this time, the first multiplexer 38) has already used up the clock pulse (CLK) with a duty of 50% as the switching control signal (CT1), so it is within one clock cycle as shown in Figure 6. Write (W) and read (R)
It is arranged so that these are performed alternately.

One embodiment of the present invention is generally constructed as described above, and its zoom-up operation will be described below by taking the case of 4x zoom (in terms of area ratio) as an example.

Now, suppose that the area (R) of the original image shown by crosshatching in Fig. 4 is enlarged and projected onto the area (S). Specify the coordinates (X, Z) of (P).

Then, from the A/D conversion circuit (17), the corresponding 2
The decimal data X, 4N%2 is output. In this data, X represents the number of clock pulses (CLK) from the left edge of the screen to the start edge (P), and data 2 represents the number of horizontal synchronizing pulses (1 (S)) from the top edge of the screen to the start edge (P). The reason why data 4x is also derived here is as follows. Namely, as shown in FIG. 5, the TCI format video data ( 41), color (C) is calculated for luminance (Y) data.
) Since the data has been completely compressed on the time axis, the time interval from the starting points P1 and P2 in Figure 5, which correspond to the same horizontal position on the display screen (Figure 4), and the reference point 01.02 is 0zP.
This is because z=4″5iT′7.

Note that data N and 4N, which will be described later, are stored in the counter (21
) (22) is exactly the same.

Each of the data X, 4N%2 is the counter (18) in Figure 2.
(19)<20), and the relationship between each load timing and video data is shown in FIG. That is, in FIG. 5, the above-mentioned item 41) is TC
Represents one field of I-format video data, (VS
) is its vertical sync pulse, (R3) is its horizontal sync pulse,
(C) is the highly time-compressed color signal data, (Y) is the baseband luminance data, and (R1) (R2) and (St) (32) are the regions (R) (S) in Fig. 4. ) respectively.

Therefore, in FIG. 2, the A/D conversion circuit (17)
The data X from is loaded into the counter (18) at the timing of the load pulse (LHL) in FIG.
is the counter (1) at the timing of the load pulse (LH3).
9), each counter then counts clock pulses (CLK). On the other hand, data 2 is loaded into the counter (20) at the timing of the load pulse (LVl), and this counter is then loaded with the horizontal synchronization pulse (R
3) Count. Also, counters (21) (22)
For (23), the area after zooming up in Fig. 4 (
Predetermined binary data N corresponding to widths n and m of S)
, 4N, and M are respectively loaded, and each load is performed at the timing of each output of the counter (18) (19)<20). In addition, each output sets flip-flops (24), (25), and (26), respectively.
Each of these free knob flops is connected to the counter (21) (
22) and (23), the switching control signals (CT3) to (CT7) and load pulses (LH2) (LV2) shown in the figure are obtained.

Now, one field worth of video data (
41) arrives at the memory (13) in FIG.
As is clear from the above explanation, the first H, V counters (31) (34) and the second H, V counters (32)
(35) operates during the period outside the horizontal and vertical synchronizing pulseless (HS) (''/S) in the above data (41), and the third
H counter (33) and third and fourth v counter (36) (
37) is the zoom area (Ss) (
St) period, but the second multiplexer (39)
is the zoom area (Sl) (
32) The second H, V counter (32) (
35). Therefore, in a period other than the zoom area, the color (C) and brightness (Y) data in the data (41) written to the memory (13) by the first H, V counter are transferred to the second H, V counter (32 bar 35). The data is read out as is and sent to the TCI decoder (9) (Fig. 1).

Next, in each period of the zoom area (SL) (32), the third H
The output of the counter (33) is sent to the second multiplexer (39)
However, during the period of one of the regions (Sl), the output of the 4th v counter (37) is derived from the third multiplexer (40) by the control signal (C70), and this is the output of the 4th v counter (37), which is ) is output via. Therefore, the above zoom area (Sl) on the C side is (13) 1st H, V counter (31)
) (34), the C data written sequentially by the 3rd H
It is addressed and read by the counter (33) and the fourth v counter (37).

In addition to being given a clock pulse (CLK) as a count input to the third H counter (33),
Count enable signal (CEH) that switches in synchronization with the above clock (high is enabled state) (615th!!
(see I) is also applied. Therefore, this counter (3
3) is 1 every two rising edges of the above clocks (CI, K).
Counts up step by step, resulting in horizontal (X)
The same address in the direction is specified twice in succession.

On the other hand, the fourth counter (37) is composed of an up/down counter, and its A knob down control signal (
As shown in Fig. 7, the UD) signal is <3H when IH period is high.
A signal that is low for a period (up operation when high) is provided. This control signal (U D ) is, for example, the eighth
As shown in the figure, a quaternary counter (42) and an inverter (43)
(44>) and an AND gate (45). Therefore, the V counter (37) counts up three times in a row and then counts down once at the falling edge of the horizontal synchronizing pulse (HS). As a result, this counter (37) is stored in the memory (13).
) in the vertical (2) direction is specified by repeating the multiple pairs twice each, with two adjacent lines as a pair.

In this way, in the zoom area (SL) on the C side, the read address from the second multiplexer (39) is the same address is output twice in the X direction, and two adjacent lines are output twice in the two directions. Since the output is repeated one by one,
This causes C to be read from the buffer memory (13).
The data corresponds to an image that has been enlarged twice in each of the X and Z directions, that is, four times in terms of area ratio. Therefore, if such a read operation is performed over the entire zoom area (31), the area (41) in the original video data (41) will eventually be
The C data sequentially written in the main direction (13) during the period (RL) is expanded to the area (Sl), read out, and sent to the TCI decoder (9).

Here, when reading the C data from the memory (13) as described above, the reason why two lines in two directions are read out as a pair is that in the MUSE output method, the narrowband chrominance signal CN and the wideband chrominance signal CN This is because the color signal Cw is sent alternately, ie, line sequentially, for each line within one field.

Next, in the period of the zoom area (Sl) on the Y side, the controller f(
C70) from the third multiplexer (40)
The output of the v counter (36) is derived, and this output
It is output by the second multiplexer (39) together with the output of the H counter (33). Therefore, in this case, the first
The Y data sequentially written by f(, V counters (31) and (34)) is addressed and read by both counters (33>(36)).

Here, the third v counter (36) is given a count enable signal (CEV>) and a signal (see FIG. 7) that switches every IH.This signal (CEV)
can also be created using the circuit shown in FIG. Therefore, this third
The v counter (36) counts up every two rising edges of the horizontal synchronizing pulse (R5), and as a result, the address for one line in two directions is specified twice. The 3H counter (33) performs exactly the same operation as in the case of reading the C data described above, and the same address in the X direction is specified twice in succession.Therefore, in the zoom area (S2) on the Y side, buffer memory (1
The Y data read from 3> is enlarged twice in the X and Z directions and appears in the same way as the C data described above. The Y data in area (R2) is expanded to area (S2), read out, and sent to the TCI dehooder (9).

Therefore, if the three primary color video signals output from the TCI decoder (9) are projected onto the picture tube, the color image in region (R) in FIG. 4 will be enlarged four times and projected in region (S). It is possible. At that time, use the joystick (see Figure 2).
15a) to change the output data X, 4X, and Z of the A/D conversion circuit (17), the zoom area (S
) can be freely set, while the counter ( in Figure 2) can be set freely.
21) Data N, 4 to be preset to (22) and (23)
By changing N and M, the above zoom area (R)
The widths n and m can be changed.

In this embodiment, the area (S) after zooming is set by presetting the data N and 4N%M. Given the CEH in the figure, the counter (2
By giving CEv as the count enable number in step 3), the width of the region (R) before zooming can be set.

Furthermore, although the above embodiment is for a 4x zoom, a circuit consisting of a hexadecimal counter (46) and various gate circuits (47) to (54) shown in FIG. 9 is used instead of the circuit shown in FIG. This makes it possible to achieve a 9x zoom (that is, 3x zoom in each of the X and Z directions), and the signal waveform diagram at this time is shown in FIG. Note that the signals required on the horizontal side are shown in parentheses in FIGS. 9 and 10. Furthermore, if the configuration is configured using a counter (55) and a ROM (56) as shown in FIG. 11, it is possible to support several types of zoom ratios.

(G) Effects of the Invention According to the receiver of the present invention, it is possible to enlarge and display a high-definition TV system image, and moreover, the processing for the enlarged display is performed according to the TCf signal format. This has the advantage that the circuit configuration can be an hour wheel and the memory can be of small capacity.

[Brief explanation of drawings]

1st r5! J is a block diagram showing a schematic configuration of an embodiment of a high-quality TV receiver according to the present invention, FIGS. 2 and 3 are block diagrams showing the internal configuration of main parts, and 4th tyJ shows a zoom display screen. Figure 5 is a diagram showing the time relationship between TCI type video data and various control signals, Figures 6 and 7 are timing diagrams for explaining the operation, and Figure 8 is the main part of the control pulse generation circuit. A circuit block diagram showing FIG. 9 is a block diagram similar to FIG. 8 in another embodiment, and FIG.
The figure is an operation timing diagram of this embodiment, and FIG. 11 shows still another embodiment. It is a figure similar to J.

Claims (1)

[Claims] (1) A TCI decoder is used in a high-definition television receiver that reproduces a color image by decoding a TCI-type high-definition video signal in which the color signal is time-base compressed and time-division multiplexed with the luminance signal. A buffer memory for storing at least one field of the video signal in the preceding stage, and a control circuit for controlling a part of the video signal stored in the memory to be read out at a slower speed than when writing. A high-definition television receiver, characterized in that a part of the image is enlarged and displayed by supplying a video signal from the memory to the decoder.