JPS6466769A - Data processing having decentralized shared memories - Google Patents
Data processing having decentralized shared memoriesInfo
- Publication number
- JPS6466769A JPS6466769A JP22310087A JP22310087A JPS6466769A JP S6466769 A JPS6466769 A JP S6466769A JP 22310087 A JP22310087 A JP 22310087A JP 22310087 A JP22310087 A JP 22310087A JP S6466769 A JPS6466769 A JP S6466769A
- Authority
- JP
- Japan
- Prior art keywords
- memories
- check
- data
- devices
- shared
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Multi Processors (AREA)
Abstract
PURPOSE:To detect the trouble of an inter-memory data transfer circuit without deteriorating the data transfer efficiency by securing such a constitution where the devices check simultaneously the data transferred among these devices at the multi-address communication and each device collates its own check result with the check results of other devices. CONSTITUTION:The signal lines are prepared for the shared memories 2-a-2-c respectively so that each of these memories can deliver the check result of its received data to a bus 3 securing the connection among those memories 2-a-2-c. Then each of these memories fetches the check results sent from other memories and accepts the data given from other memories only when its own deciding result is correct and when it is decided that at least one of other memories is correct. Otherwise the errors are decided. Furthermore the shared memory of the data output origin performs the prescribed frequency of retries in case at least one of those shared memories including its own one has the wrong check result. Thus it is possible to detect the trouble area as long as this area is the only one.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223100A JPH0658664B2 (en) | 1987-09-08 | 1987-09-08 | Data processing device with distributed shared memory |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP62223100A JPH0658664B2 (en) | 1987-09-08 | 1987-09-08 | Data processing device with distributed shared memory |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS6466769A true JPS6466769A (en) | 1989-03-13 |
JPH0658664B2 JPH0658664B2 (en) | 1994-08-03 |
Family
ID=16792826
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62223100A Expired - Lifetime JPH0658664B2 (en) | 1987-09-08 | 1987-09-08 | Data processing device with distributed shared memory |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0658664B2 (en) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60178572A (en) * | 1984-02-27 | 1985-09-12 | Toshiba Corp | Multiprocessor device |
JPS6257049A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
-
1987
- 1987-09-08 JP JP62223100A patent/JPH0658664B2/en not_active Expired - Lifetime
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60178572A (en) * | 1984-02-27 | 1985-09-12 | Toshiba Corp | Multiprocessor device |
JPS6257049A (en) * | 1985-09-06 | 1987-03-12 | Nec Corp | Decentralized processor system |
Also Published As
Publication number | Publication date |
---|---|
JPH0658664B2 (en) | 1994-08-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
EP0219413A3 (en) | An array reconfiguration apparatus and method particularly adapted for use with very large scale integrated circuits | |
GB1400631A (en) | Programme controlled data processing systems | |
MY112277A (en) | Connectable electronic device | |
SE8402299L (en) | SIGNAL TRANSMISSION SYSTEM | |
US5297261A (en) | Multiprocessor system with power-on reset function | |
JPS6466769A (en) | Data processing having decentralized shared memories | |
EP0044218A1 (en) | Data communication system | |
MY111292A (en) | Data bus. | |
EP0283564A3 (en) | Memory re-mapping in a microcomputer system | |
CA2151673A1 (en) | Parallel Processing System with a Plurality of Communication Register Modules | |
JPH0132143Y2 (en) | ||
JPS5676826A (en) | Data transfer control system | |
JPS55136748A (en) | Parameter set system for data communication unit | |
Downing et al. | The FASTBUS segment interconnect | |
JPS5676827A (en) | Data transfer control system | |
DE3786413T2 (en) | Memory gate circuit for an error signal scanner. | |
JPS57212843A (en) | Signal transmitting system | |
JPS5493903A (en) | Test system for backup circuit | |
JPS6410377A (en) | Inter-module communication system | |
Richter | Processing System with Dual Buses | |
JPS6466741A (en) | Bus line transmission system | |
JPS55108068A (en) | Memory control system | |
GB1484472A (en) | Arrangements for securing data transfers in a communication system | |
JPS5244531A (en) | Error detection/correction system for memory | |
JPS5574620A (en) | Noise suppression system for data bus |