JPH0658664B2 - Data processing device with distributed shared memory - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a multi-computer system having a shared memory, and in particular, the memory is distributedly installed in each computer, and the contents are realized by broadcast communication between the memories. The present invention relates to a data processing device suitable for a shared memory device that performs matching.

[Prior art]

Examples of the distributed shared memory include JP-A-57-189257 and JP-A-58-35624. The former is a computer system in which a plurality of CPUs are provided and a shared memory unique to each CPU is connected. The latter describes the transfer circuit failure diagnosis on the bidirectional data bus.

[Problems to be solved by the invention]

Each information processing device (hereinafter referred to as CPU) has its own memory, and when writing to the memory, the contents of each memory are made consistent by performing broadcast transfer, and shared by each memory. In a distributed shared memory system having a memory function, the degree of coincidence of the contents of memory has a great influence on the reliability of the entire system. That is, for example, when considering a system in which three CPUs each have a shared memory, if one arbitrary data receiving circuit or transmitting circuit has a failure, the content of that shared memory is the content of another shared memory. If the system is operated in this state, the shared data cannot be sent / received in the multi-system only for the relevant CPU, resulting in a very dangerous state. Therefore, in order to solve the above-mentioned problems, it is indispensable to immediately detect the faulty part and report the abnormality to the CPU.

In the above-mentioned Japanese Patent Laid-Open No. 57-189257, no consideration is given to a failure during data transfer. Further, Japanese Patent Laid-Open No. 58-35624 describes transfer circuit failure diagnosis on a bidirectional data bus, but according to this example, a data receiving device is selected by addressing for self-diagnosis. Therefore, there is a problem in that the transfer efficiency is lowered in a system in which one device, which is the object of the present invention, performs broadcast transfer to a plurality of devices.

An object of the present invention is to solve the above-mentioned problems of the prior art and to provide a data processing device having a distributed shared memory suitable for being applied to a multi-computer system.

[Means for solving problems]

According to the present invention, each device simultaneously checks transfer data at the time of broadcast communication between devices (computers, the same applies below), collates the check results of its own with the check results of devices other than itself, and verifies its own validity. A means to reasonably judge is provided in the shared memory.

[Action]

On the bus connecting the devices, prepare a signal line for each device to output the result of checking the received data for each device, and each device captures the check result output by the other device and Accept data from other devices only when it is correct and at least one of the other devices determines that it is correct, and otherwise judge it as an error.
In addition, the data output source performs a predetermined number of retries when the check result of at least one memory device including itself is incorrect. As a result, if the determination result is an error even after retrying, the failure location can be determined as follows.

That is, the output circuit of the data output device has a failure when a plurality of devices including itself has determined an error, and the reception circuit of the device has a failure when only one device has an error.

According to the above judgment method, if there is only one failure point,
The device can reasonably detect the part.

〔Example〕

FIG. 2 shows the overall configuration of a system which is an embodiment of the present invention.

Each of the CPUs 1-a to 1-c has a shared memory (GM) 2-
a to 2-c, and the shared memories are connected to each other by a bus 3. Further, the CPUs 1-a to 1-c are connected to the private memory 50- via the buses 60-a to 60-c.
a to 50-c. Private memory (PM)
Each of the CPUs stores a program and data for one CPU, and the GM stores data common to a plurality of CPUs.
The data from PM and GM is taken into the CPU along with the operation of the equipment, the data is processed, and the data of the own CPU is PM.
Common data that you want to write to and then pass to another CPU is G
Write to M.

Now, for example, if the CPU 1-a writes data to the shared memory 2-a, the copy function of the shared memory 2-a causes the same data in the other shared memories 2-b and 2-c via the bus 3. The same data is written in the address. Therefore, the CPUs 1-a to 1-c can share data with other CPUs only by accessing only the shared memory connected thereto.

Now, FIG. 1 shows a shared memory 2 (2-a ...
Since 2-c have the same hardware, they are commonly referred to as shared memory 2 hereinafter. ) Is a diagram showing the inside.

The operation of the shared memory 2 will be described below with reference to FIG.

Data reading from the CPU 1 is performed as follows.
That is, the memory address is output to the address signal 4,
A READ signal 8 for reading is output. The address passes through the gate 11 and is selected by the selector 21 to specify the address of the memory 23. The READ signal 8 is input to the selection circuit 24 through the gate 16. Selection circuit 24
Is a circuit that reads and writes the memory while selecting only one of the three input signals 16-1, 17-1, 27-1 and returning the response. When selecting the input signal 16-1, the memory is Read signal 24-2 and response signal 24-2 are output. When input signal 17-1 is selected, memory write signal 24-1 and response signal 24-4 are output, input output 27-
When 1 is selected, the memory write signal 24-1 and the response signal 24-3 are output.

As a result, the memory 23 is read out, its output is input to the gate 13, and the data is output to the bus 5 because the gate 13 is enabled by the signal 16-1.
It reaches PU. The CPU knows that the reading of the data is completed by the response signal 6 given through the gate 14, and stops the READ signal 8. The explanation goes back and forth,
The selectors 21 and 22 are adapted to select the B side input by the signal 24-b only while the signal 27-1 is selected, and accordingly, when the CPU accesses (signal 16-1 or signal 17-1). Is selected), select the A side input.

Next, data writing from the CPU is performed as follows. The address signal 4, the data signal 5, and the WRITE signal 9 for writing are output from the CPU 1. The address and the data pass through the gates 11 and 12 and are selected by the selectors 21 and 22 to be the address and the input data of the memory 23, respectively. WRITE signal 9 is gate 17
The result signal 24-1 selected by the selection circuit 24 passes through the memory 23 and the response signal 24-4 is transmitted to the gate 15
Is output to the CPU 1 via. The CPU 1 thereby knows the end of writing and stops the WRITE signal 9. During this time, the following things are done at the same time. That is, the address and data passed through the gates 11 and 12 are given to the store buffer 19 and further stored in the store buffer 19 by the signal 17-1. Well, store store 19
Is a first-in first-out memory, and when data is stored in the self, the signal 19-
3 is output and the data is read by the signal 18-1,
The output of the signal 19-3 stops when all the signals are exhausted. When receiving the signal 19-3, the bus control circuit 18 outputs the occupancy request signal 18-2 to the bus 3. Although the specific description of the occupancy control of the bus 3 is not disclosed because it is not directly involved in the present invention, when the bus 3 is occupied, the occupancy signal 18-3 is output to the bus while the signal 18-1 is output. The signal 18-1 becomes a read signal to the store buffer 19, and at the same time, the gate 3
1 and 32 are enabled, and the contents of the store buffer, that is, the memory address and its data are output to the bus 3. Further, the timing circuit 20 generates a write timing, and the write signal 33− is sent to the bus 3 via the gate 33.
1 is output. As a result, the shared memory 2 further performs the following operation, but the operation described below is performed simultaneously for all the shared memories 2 connected to the bus 3. That is, the address and data output from the gates 31 and 32 are transferred to the gates 34 and 3 via the bus 3, respectively.
5 and the signal 33-1 is also commonly received by the gate 38.

Now, the address and data received by the gates 34 and 35 are output from the gate 38 to the respective registers 2 and 3.
5 and 26, and the output signal of the gate 38 sets a flip-flop 27 (hereinafter abbreviated as FF27). As a result, the signal 27-1 is output and the selection circuit 24
And a busy signal 39-1 is output to the bus 3 via the gate 39. The selection circuit 24 outputs the signal 27-1.
Is selected, the B input of the selectors 21 and 22 is selected by the signal 24-6, the write signal 24-1 is output, and the response signal 24-3 is further output.
The data is written to the memory 23, and the FF
27 is reset and the busy signal 39-1 stops.

Although not described so far, in the embodiment, all the data lines 5, the memory 23, the store buffer 19, and the bus 3 have parity bits for data. Then, the register 26 performs parity check on the data received from the bus 3 and outputs an error signal when there is an error, so that the gates 36 and 37 send either an error signal or a normal signal to an individual line on the bus. Is output. Next, the operation returns to the operation of the shared memory on the side transmitting the data again. The busy signal 39-1 and the error signal 36-
1 to 3 can receive it if someone on the bus outputs it. The signals 36-4 to 36-6 are normal signals forming a pair with the signals 36-1 to 36-3. The busy signal is used to detect that all of the shared memories have finished operating, and the error signal is used to detect that someone is detecting an error. That is, when the output of the gate 40 stops, the bus control circuit 18 regards it as the end of one transfer and releases the bus occupation. However, if any of the signals 36-1 to 36-3 is present at this time, the determination circuit The signal 42-1 is output from 42, the retry signal 18-4 is output, and the write signal is output again.

As described above, no matter which occupied memory on the bus 3 causes a reception error, the retry is executed and the data in all the shared memories are kept consistent.

Now, referring to FIG. 1, the features of the embodiment of the present invention are:
As a result of the parity check of the data received from bus 3,
Both error and normal are output, and each of the above signals is on an individual line on the bus 3, and the shared memory 2
Is receiving all errors including self, normal signal,
Furthermore, a judging circuit 42 for judging the presence or absence of an error by collating the pattern of the above signals is added.

Focusing on the above-mentioned individual lines, as shown in FIG. 4, the signals output by each of the individual lines are connected so as to be input to a fixed position of the determination circuit. Further, to the determination circuit 42,
Bus occupancy signal 1 to indicate that you are now occupying the bus
A signal 18-1 triggered by 8-3 is given, and this signal can detect that the user is now transmitting data to the bus 3. Then, the determination circuit 42 makes the following determination.

(1) If the self is the sender and at least one error signal is received, the signal 42-1 is output to perform the retry, and the bus control circuit 18 is made to retry.

(2) When the self is the sender and the last retry is performed, when all error signals are received, the self is regarded as a failure, the signal 42-2 is output, and the failure is reported to the CPU.

(3) Regardless of whether the user is the sender or the receiver, the signal from the bus 3 is stored in the memory by the signal 42-3 except when the result of the check made by the user is normal and one other person outputs a normal signal. Writing to 23 is prohibited.

(4) Regardless of whether the sender is the sender or the recipient, if only the check result of the self is an error at the last retry, the self is regarded as a failure and the signal 42-2 is output.

According to the above judgment logic, the following failures can be correctly judged. That is, in the case shown in FIG.
Assuming that it is −a, when the transmission circuit of 2-a fails, 2-a becomes a failure by the following decision logic (2), and 2-b and 2-c write by the decision logic (3). Not performed.

When the receiving circuit of 2-b is faulty, 2-a and 2-c are decision logics.
Writing is performed according to (3), but writing is not performed for 2-b.
Further, 2-a retries by (1), but finally 2-b detects its own failure by the decision logic (4).

In addition, although the description will be changed, in FIG. 1, the bus control circuit 1
When a predetermined retry is carried out, 8 outputs a signal 43-1 on the bus through the final retry execution time gate 43, and all shared memories receive the signal and fetch it into the decision circuit 42. There is.

Although the specific circuit of the determination circuit 42 is not shown,
The above-mentioned decision logic is a known technique as it can be realized by a simple combination of AND and OR.

According to the present embodiment, the failed shared memory can report its own failure to the CPU, so that it is possible to reliably prevent the CPU from erroneously using data that does not match other memory.

FIG. 3 shows a second embodiment of the present invention.

In FIG. 3, the main points different from the embodiment of FIG. 1 are as follows.

(1) If only the error signal is output to the bus as a result of the reception data determination, and the self is the sender, the gate 3
Do not suppress the output of 6 and output an error signal to the bus.

(2) The error signal must be a common signal line for all shared memory devices.

On the other hand, those having the same number have the same function. still,
In FIG. 1, the failure detection is performed by the determination circuit 42, but in the embodiment of FIG. 3, it is performed in the bus control circuit 18.

The embodiment shown in FIG. 3 employs a method of detecting its own failure only when it becomes a sender. That is, when the self is the sender, the data transmitted by the self is received by the register 26, and the error signal 26-1 which is the error judgment result, the error signal on the bus 6, that is, the gate 4
The output of 1 is collated by the bus control circuit 18. When performing this collation, failure diagnosis is performed using the following judgment logic.

(1) If the self-determination result and the determination results of other memories are accompanied by an error, it is determined that the transmission circuit of the self is defective.

(2) When the judgment result of its own is an error and the judgment result of other memory is not an error, it is regarded as its own receiving circuit failure.

When the self failure is detected as described above, the bus control circuit 18
Outputs an error signal 42-2 to report the failure to the CPU.

According to the present embodiment, the failure of itself can be detected only by the sender, but since the signal line of the bus can be shared as compared with FIG. 1, it is possible to improve the expandability. it can. However, it goes without saying that a failure can be detected in advance by ensuring that an arbitrary area of the shared memory is reserved for maintenance and each CPU sequentially writes data to that area.

〔The invention's effect〕

According to the present invention, failure detection of a data transfer circuit between memories, which has not been considered in the prior art, can be performed without lowering the data transfer efficiency.

[Brief description of drawings]

FIG. 1 is an internal circuit diagram of a shared memory which is an embodiment of the present invention, and FIG. 2 is a system configuration diagram which is an embodiment of the present invention.
FIG. 3 is an internal circuit diagram of the shared memory according to the second embodiment of the present invention, FIG. 4 is a connection diagram between the shared memories in the second embodiment, and FIG. 5 is an operation explanation of the second embodiment. It is a block diagram for the. 36 ... Error detection signal output gate, 37 ... Normal detection signal output gate, 42 ... Judgment circuit (fault and error rationality judgment circuit).

Continuation of the front page (56) References JP 62-57049 (JP, A) JP 62-57048 (JP, A) JP 60-178572 (JP, A)

Claims (1)

[Claims] 1. A common bus, a plurality of shared memories connected in parallel to the common bus, and a plurality of CPUs connected to each of the shared memories.
U is a data processing having a distributed shared memory that constitutes one computer and broadcasts data from any one computer to other computers via the common bus. In the apparatus, each shared memory includes a determination unit that determines whether the data received from the common bus at the time of the broadcast transfer is correct, a unit that puts the determination result of the determination unit on the common bus, an error determination result of itself, and the common bus. A data processing device having a distributed shared memory, which is provided with a means for checking whether or not an error has occurred and for detecting a faulty part by collating with a determination result of an error other than its own sent via.