JPS6464362A - Bias adjustment circuit - Google Patents

Abstract

PURPOSE:To obtain a stable bias signal by a method wherein a signal to be adjusted from a charge storage device is retained for a prescribed duration, the signal is integrated within a retention duration in a delay means and a level of a direct-current bias point of the signal retained in the delay means is shifted. CONSTITUTION:A signal R(t) to be delayed is fed to an input circuit 12 of a delay element 13 via a coupling capacitor 11 ; a connection contact P is pulled up to a definite voltage VD via a resistor 14. A sample-and-hold circuit 16 samples and holds an output signal R'(t) whose impedance has been converted in an output circuit 15 while it is synchronized with a duration during which the delay element 13 transfers one signal charge. An amplifier 17 amplifies a signal retained in the sample-and-hold circuit 16 and outputs it to an output terminal 18. Furthermore, an input circuit 19 is connected to an amplifier 21 via an integration stage 20, and is connected to a reset terminal 22; when a reset signal RS is impressed, an output is clamped at a prescribed potential irrespective of a signal from the integration stage 20. A sample- and-hold circuit 23 samples and holds a signal output from the amplifier 21 and amplifies it; the signal is fed to a control terminal of the output circuit 15 as a control signal SC for bias adjustment use.