JPS6464339A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS6464339A
JPS6464339A JP62221410A JP22141087A JPS6464339A JP S6464339 A JPS6464339 A JP S6464339A JP 62221410 A JP62221410 A JP 62221410A JP 22141087 A JP22141087 A JP 22141087A JP S6464339 A JPS6464339 A JP S6464339A
Authority
JP
Japan
Prior art keywords
superconductive
layer
metallic layer
oxide ceramic
whole surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62221410A
Other languages
Japanese (ja)
Other versions
JP2553101B2 (en
Inventor
Kuniyoshi Yoshikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP62221410A priority Critical patent/JP2553101B2/en
Publication of JPS6464339A publication Critical patent/JPS6464339A/en
Application granted granted Critical
Publication of JP2553101B2 publication Critical patent/JP2553101B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
    • H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
    • H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
    • H01L2224/02165—Reinforcing structures
    • H01L2224/02166—Collar structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Superconductor Devices And Manufacturing Methods Thereof (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To obtain a superconductive characteristic which is stable for a long-term use, by using superconductive materials to form an electrode wiring for connection between respective contact electrodes of semiconductor elements and besides covering these electrodes wirings with conductive layers. CONSTITUTION:Superconductive materials such as oxide ceramic high-temperature superconductive materials containing copper, oxygen, alkaline earth metal, rare earth metal are piled on the whole surface of a substrate to form an oxide ceramic high- temperature superconductive layer 110. In succession, this substrate is provided with heat treatment to have a superconductive characteristic and it is processed to have desired wiring patterns and to form electrode wirings. Next an insulation layer 111 is formed on the whole surface and then an opening is formed to draw the high- temperature superconductive Iayer 110 outside. A metallic layer 112 containing Al or the like, for example, is formed on the opening. This metallic layer 112 is used to cover the oxide ceramic high-temperature superconductive layer 110 at an outer electrode drawing part. Thereafter a PSG film 113 for example is formed as an insulation film for use in protection on the whole surface, and next it is selectively etched to form an opening part 114 for use in drawing an pad electrode on the metallic layer 112. A bonding wire 115 is pressed/stuck on an exposed surface of the metallic layer 112.
JP62221410A 1987-09-04 1987-09-04 Semiconductor device Expired - Fee Related JP2553101B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62221410A JP2553101B2 (en) 1987-09-04 1987-09-04 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62221410A JP2553101B2 (en) 1987-09-04 1987-09-04 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS6464339A true JPS6464339A (en) 1989-03-10
JP2553101B2 JP2553101B2 (en) 1996-11-13

Family

ID=16766302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62221410A Expired - Fee Related JP2553101B2 (en) 1987-09-04 1987-09-04 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2553101B2 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234575A (en) * 1987-03-24 1988-09-29 Agency Of Ind Science & Technol Formation of pattern of superconducting circuit
JPS63300536A (en) * 1987-05-29 1988-12-07 Nec Corp Superconducting wiring
JPS6420638A (en) * 1987-07-15 1989-01-24 Sharp Kk Wiring of semiconductor device
JPS6445144A (en) * 1987-08-13 1989-02-17 Semiconductor Energy Lab Manufacture of superconducting device
JPS6453433A (en) * 1987-03-27 1989-03-01 Hitachi Ltd Semiconductor integrated circuit

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63234575A (en) * 1987-03-24 1988-09-29 Agency Of Ind Science & Technol Formation of pattern of superconducting circuit
JPS6453433A (en) * 1987-03-27 1989-03-01 Hitachi Ltd Semiconductor integrated circuit
JPS63300536A (en) * 1987-05-29 1988-12-07 Nec Corp Superconducting wiring
JPS6420638A (en) * 1987-07-15 1989-01-24 Sharp Kk Wiring of semiconductor device
JPS6445144A (en) * 1987-08-13 1989-02-17 Semiconductor Energy Lab Manufacture of superconducting device

Also Published As

Publication number Publication date
JP2553101B2 (en) 1996-11-13

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees