JPS6461018A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS6461018A
JPS6461018A JP21945187A JP21945187A JPS6461018A JP S6461018 A JPS6461018 A JP S6461018A JP 21945187 A JP21945187 A JP 21945187A JP 21945187 A JP21945187 A JP 21945187A JP S6461018 A JPS6461018 A JP S6461018A
Authority
JP
Japan
Prior art keywords
layer
film
iii
compound semiconductor
arsenide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP21945187A
Other languages
Japanese (ja)
Inventor
Akihiko Okamoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP21945187A priority Critical patent/JPS6461018A/en
Publication of JPS6461018A publication Critical patent/JPS6461018A/en
Pending legal-status Critical Current

Links

Landscapes

  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To improve the bondability of a silicon dioxide film with III-V compound semiconductor layer by forming a III-V compound semiconductor film containing aluminum between the silicon dioxide layer and the III-V compound semiconductor layer. CONSTITUTION:An n-type gallium indium arsenide layer 2 is grown on a semi- insulating InP substrate 1, and indium aluminum arsenide film 4 is grown thereon. An SiO2 film 3 and the film 4 are etched to form an opening 5 for a base layer and an emitter layer. A p-type gallium indium arsenide layer 6 and an n-type indium aluminum arsenide layer 7 are formed. The layer 7 is mesa etched, and electrodes 8, 9, 10 are formed. The base layer made of the layer 6 on the film 3 becomes a polycrystalline, and the bondability to the film 3 is improved due to the presence of the film 4.
JP21945187A 1987-09-01 1987-09-01 Manufacture of semiconductor device Pending JPS6461018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP21945187A JPS6461018A (en) 1987-09-01 1987-09-01 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP21945187A JPS6461018A (en) 1987-09-01 1987-09-01 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS6461018A true JPS6461018A (en) 1989-03-08

Family

ID=16735625

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21945187A Pending JPS6461018A (en) 1987-09-01 1987-09-01 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS6461018A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101429A (en) * 1990-08-20 1992-04-02 Matsushita Electric Ind Co Ltd Hetero junction bi-polar transistor and manufacture thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04101429A (en) * 1990-08-20 1992-04-02 Matsushita Electric Ind Co Ltd Hetero junction bi-polar transistor and manufacture thereof

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