JPS645546U - - Google Patents
Info
- Publication number
- JPS645546U JPS645546U JP10015387U JP10015387U JPS645546U JP S645546 U JPS645546 U JP S645546U JP 10015387 U JP10015387 U JP 10015387U JP 10015387 U JP10015387 U JP 10015387U JP S645546 U JPS645546 U JP S645546U
- Authority
- JP
- Japan
- Prior art keywords
- data signal
- internal
- circuit
- signal
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Maintenance And Management Of Digital Transmission (AREA)
Description
第１図は本考案の一実施例によるデイジタルル
ープバツク回路の説明図、第２図は第１図に示す
各信号のタイムチヤートを示す図、第３図は従来
のデイジタルループバツク回路の説明図、第４図
は第３図に示す各信号のタイムチヤートである。
１：データ転送遅延回路、ｓｄ：内部送信デー
タ信号、ｒｄ：内部受信データ信号、ｃｓ：内部
送信可信号、ｒｓ：内部送信要求信号、ｃｄ：内
部キヤリア検出信号。
Fig. 1 is an explanatory diagram of a digital loopback circuit according to an embodiment of the present invention, Fig. 2 is a diagram showing a time chart of each signal shown in Fig. 1, and Fig. 3 is an explanatory diagram of a conventional digital loopback circuit. , FIG. 4 is a time chart of each signal shown in FIG. 3. 1: data transfer delay circuit, sd: internal transmission data signal, rd: internal reception data signal, cs: internal transmission enable signal, rs: internal transmission request signal, cd: internal carrier detection signal.
Claims (1)
変復調側のデータ信号折返部を介して送信側に折
返すデイジタルループバツク回路において、 受信側からの内部キヤリア検出信号がオン状態
になつた後、内部受信データ信号を一時記憶し、
内部送信可信号がオン状態となつた後、記憶した
内部受信データ信号を内部送信データ信号として
送信側へ出力するデータ転送遅延回路を前記デー
タ信号折返部に設けたことを特徴とするデイジタ
ルループバツク回路。[Scope of Claim for Utility Model Registration] In a digital loopback circuit that returns a digital data signal output from the receiving side to the transmitting side via a data signal folding section on the modulation/demodulation side, an internal carrier detection signal from the receiving side is in an on state. After the internal reception data signal is temporarily stored,
A digital loopback characterized in that the data signal return section is provided with a data transfer delay circuit that outputs the stored internal reception data signal to the transmission side as an internal transmission data signal after the internal transmission enable signal is turned on. circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10015387U JPS645546U (en) | 1987-06-30 | 1987-06-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10015387U JPS645546U (en) | 1987-06-30 | 1987-06-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS645546U true JPS645546U (en) | 1989-01-12 |
Family
ID=31327968
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10015387U Pending JPS645546U (en) | 1987-06-30 | 1987-06-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS645546U (en) |
-
1987
- 1987-06-30 JP JP10015387U patent/JPS645546U/ja active Pending
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