JPS6280448U - - Google Patents
Info
- Publication number
- JPS6280448U JPS6280448U JP17085185U JP17085185U JPS6280448U JP S6280448 U JPS6280448 U JP S6280448U JP 17085185 U JP17085185 U JP 17085185U JP 17085185 U JP17085185 U JP 17085185U JP S6280448 U JPS6280448 U JP S6280448U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- loop test
- output
- circuit
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005540 biological transmission Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図は本考案の実施例のループテスト回路図
、第２図は従来例のループテスト回路図、第３図
は本考案の動作チヤートである。
１：変調回路、６：受信キヤリア復調器、７：
レベル検出器、８：復調出力回路、９：キヤリア
検出出力回路、１０：データ送信制御回路、１２
：外部端末装置、１４：アナログループ器、２０
：送信キヤリア制御信号、２１：送信データ、２
２：アナログループテスト指定信号、２３：復調
出力信号、２４：キヤリア検出出力信号、２５：
データ送信制御出力信号。
FIG. 1 is a loop test circuit diagram of an embodiment of the present invention, FIG. 2 is a loop test circuit diagram of a conventional example, and FIG. 3 is an operation chart of the present invention. 1: Modulation circuit, 6: Receiving carrier demodulator, 7:
Level detector, 8: Demodulation output circuit, 9: Carrier detection output circuit, 10: Data transmission control circuit, 12
: External terminal device, 14: Analog loop device, 20
: Transmission carrier control signal, 21: Transmission data, 2
2: Analog loop test designation signal, 23: Demodulation output signal, 24: Carrier detection output signal, 25:
Data transmission control output signal.
Claims (1)
側ループテスト機能を所有している変復調装置に
おいて、ＤＡＴＡモード時は端末側からのアナロ
グループテスト指定信号とキヤリア検出出力信号
の積により、復調出力回路から端末側にアナログ
ループテスト信号を出力すると共に、アナログル
ープテスト指定信号が入力している間はキヤリア
検出出力信号が無しの状態で出力する回路構成と
し、ＴＥＳＴモード時は受信キヤリアの一定レベ
ル条件と、さらに復調出力信号とキヤリア検出出
力信号とデータ送信制御出力信号の積により変調
回路を制御し、変調回路からＬＩＮＥ側ループテ
スト信号を出力すると共に、端末側に復調出力信
号、キヤリア検出信号、データ送信制御出力信号
が無しの状態で出力する回路構成としていること
を特徴とするループテスト回路。 Terminal side analog loop test function and LINE
In a modem that has a side loop test function, in DATA mode, an analog loop test signal is output from the demodulation output circuit to the terminal side based on the product of the analog loop test designation signal from the terminal side and the carrier detection output signal. , the circuit is configured so that no carrier detection output signal is output while the analog loop test designation signal is input, and in the TEST mode, the received carrier has a certain level condition, and the demodulation output signal and carrier detection output signal The modulation circuit is controlled by the product of the data transmission control output signals, and the LINE side loop test signal is output from the modulation circuit, and the demodulation output signal, carrier detection signal, and data transmission control output signal are output to the terminal side without any. A loop test circuit characterized by a circuit configuration.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17085185U JPS6280448U (en) | 1985-11-08 | 1985-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17085185U JPS6280448U (en) | 1985-11-08 | 1985-11-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6280448U true JPS6280448U (en) | 1987-05-22 |
Family
ID=31105942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17085185U Pending JPS6280448U (en) | 1985-11-08 | 1985-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6280448U (en) |
-
1985
- 1985-11-08 JP JP17085185U patent/JPS6280448U/ja active Pending
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