JPS6280451U - - Google Patents
Info
- Publication number
- JPS6280451U JPS6280451U JP17181685U JP17181685U JPS6280451U JP S6280451 U JPS6280451 U JP S6280451U JP 17181685 U JP17181685 U JP 17181685U JP 17181685 U JP17181685 U JP 17181685U JP S6280451 U JPS6280451 U JP S6280451U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- output
- outputs
- frequency
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
Description
第１図は本考案によるＰＳＫ復調受信機の構成
図、第２図は従来のＰＳＫ復調受信機の構成図で
ある。
１は入力端子、２はクロツク出力端子、３はデ
ータ出力端子、４は受信回路、５は検波回路、６
は逓倍回路、７はタンク回路、８は分周回路、９
はデータ再生回路、１０はＡＧＣ制御信号、１１
は再生搬送波信号、１２は判定回路である。図中
、同一又は相当するものは、同一符号を付して示
してある。
FIG. 1 is a block diagram of a PSK demodulation receiver according to the present invention, and FIG. 2 is a block diagram of a conventional PSK demodulation receiver. 1 is an input terminal, 2 is a clock output terminal, 3 is a data output terminal, 4 is a receiving circuit, 5 is a detection circuit, 6
is a multiplier circuit, 7 is a tank circuit, 8 is a frequency divider circuit, 9
is a data reproducing circuit, 10 is an AGC control signal, 11
1 is a reproduced carrier wave signal, and 12 is a determination circuit. In the figures, the same or equivalent parts are indicated by the same reference numerals.
Claims (1)
変換して、ＰＳＫのベースバンド信号を出力する
受信回路と、入力信号の信号レベルを検波し、受
信回路の出力レベルが一定となる様にＡＧＣ信号
を出力する検波回路と、上記受信回路のベースバ
ンド出力信号を逓倍する逓倍回路と、上記逓倍回
路の出力信号のうち、所要信号のみを狭帯域に取
り出すためのタンク回路と、上記タンク回路の出
力信号を分周し、ＰＳＫ変調波の搬送波を再生し
、かつクロツク信号を出力する分周回路と、上記
検波回路の出力であるＡＧＣ制御信号の値により
分周回路にリセツトパルスを出力する判定回路と
、上記受信回路の出力であるベースバンド信号と
、分周回路の出力信号からデータを再生するデー
タ再生回路を備えたことを特徴とするＰＳＫ復調
受信機。 A receiving circuit that receives a PSK modulated high frequency signal, converts the frequency, and outputs a PSK baseband signal, and a receiving circuit that detects the signal level of the input signal and outputs an AGC signal so that the output level of the receiving circuit is constant. A detection circuit for outputting, a multiplier circuit for multiplying the baseband output signal of the receiving circuit, a tank circuit for extracting only the desired signal in a narrow band from among the output signals of the multiplier circuit, and an output signal of the tank circuit. a frequency divider circuit that divides the frequency of the PSK modulated wave, reproduces the carrier wave of the PSK modulated wave, and outputs a clock signal; and a determination circuit that outputs a reset pulse to the frequency divider circuit based on the value of the AGC control signal that is the output of the detection circuit. A PSK demodulating receiver, comprising a data reproducing circuit that reproduces data from a baseband signal that is the output of the receiving circuit and an output signal of the frequency dividing circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17181685U JPS6280451U (en) | 1985-11-08 | 1985-11-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17181685U JPS6280451U (en) | 1985-11-08 | 1985-11-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6280451U true JPS6280451U (en) | 1987-05-22 |
Family
ID=31107793
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17181685U Pending JPS6280451U (en) | 1985-11-08 | 1985-11-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6280451U (en) |
-
1985
- 1985-11-08 JP JP17181685U patent/JPS6280451U/ja active Pending
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