JPS61191656U - - Google Patents

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Publication number
JPS61191656U
JPS61191656U JP7495985U JP7495985U JPS61191656U JP S61191656 U JPS61191656 U JP S61191656U JP 7495985 U JP7495985 U JP 7495985U JP 7495985 U JP7495985 U JP 7495985U JP S61191656 U JPS61191656 U JP S61191656U
Authority
JP
Japan
Prior art keywords
detection circuit
modulation
reception
signal
demodulation device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7495985U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7495985U priority Critical patent/JPS61191656U/ja
Publication of JPS61191656U publication Critical patent/JPS61191656U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の実施例の受信データ起動検出
回路、第２図、第３図は従来の受信データ起動検
出回路、第４図は第１図の動作説明図である。 １：受信端、２：ＣＤ出力、３：ＲＤ出力、４
：ＲＤ復調回路、５：ＣＤ検出回路、６：ＣＤ検
出レベル設定用ストラツプ、７：減衰器、８：ア
ンド素子、９：ＨＩＴ回路。 FIG. 1 is a received data activation detection circuit according to an embodiment of the present invention, FIGS. 2 and 3 are conventional reception data activation detection circuits, and FIG. 4 is an explanatory diagram of the operation of FIG. 1. 1: Receiving end, 2: CD output, 3: RD output, 4
: RD demodulation circuit, 5: CD detection circuit, 6: CD detection level setting strap, 7: attenuator, 8: AND element, 9: HIT circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 変復調装置の受信データ起動検出回路を、受信
レベル検出回路と、この受信レベル検出回路に並
設した着信レベル変化検出回路と、前記両検出回
路の出力端に接続したアンド素子とで構成し、雑
音信号とこの雑音信号とこの雑音信号に重畳して
入力する変調信号とのレベル差を検出し、この検
出点を受信データ起動点としたことを特徴とする
変復調装置。 The reception data activation detection circuit of the modulation/demodulation device is composed of a reception level detection circuit, an incoming level change detection circuit installed in parallel with this reception level detection circuit, and an AND element connected to the output terminals of both of the detection circuits. A modulation/demodulation device characterized in that a level difference between a signal, this noise signal, and a modulated signal superimposed on the noise signal and input is detected, and this detection point is used as a reception data starting point.
JP7495985U 1985-05-22 1985-05-22 Pending JPS61191656U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7495985U JPS61191656U (en) 1985-05-22 1985-05-22

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7495985U JPS61191656U (en) 1985-05-22 1985-05-22

Publications (1)

Publication Number Publication Date
JPS61191656U true JPS61191656U (en) 1986-11-28

Family

ID=30615733

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7495985U Pending JPS61191656U (en) 1985-05-22 1985-05-22

Country Status (1)

Country Link
JP (1) JPS61191656U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145272A (en) * 1982-02-22 1983-08-30 Ricoh Co Ltd Signal demodulation system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58145272A (en) * 1982-02-22 1983-08-30 Ricoh Co Ltd Signal demodulation system

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