JPS6179872U - - Google Patents
Info
- Publication number
- JPS6179872U JPS6179872U JP16376784U JP16376784U JPS6179872U JP S6179872 U JPS6179872 U JP S6179872U JP 16376784 U JP16376784 U JP 16376784U JP 16376784 U JP16376784 U JP 16376784U JP S6179872 U JPS6179872 U JP S6179872U
- Authority
- JP
- Japan
- Prior art keywords
- limiter
- output
- signal demodulator
- demodulation
- carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 1
Description
第１図は本考案の一実施例の構成を示すブロツ
ク図、第２図はキヤリア検出回路の一例を示すブ
ロツク図、第３図は従来の複数系統の復調回路を
備えた従来のＦＭ信号復調器の一例を示すブロツ
ク図、第４図は第３図における再生ＲＦ信号のス
ペクトラムである。
７，９…リミツタ、８，１０…復調回路、１５
，１６…キヤリヤレベル検出回路、１９…増幅器
、２０…検波回路、２２…比較器、２３…時定数
回路。
Fig. 1 is a block diagram showing the configuration of an embodiment of the present invention, Fig. 2 is a block diagram showing an example of a carrier detection circuit, and Fig. 3 is a conventional FM signal demodulation system equipped with conventional demodulation circuits of multiple systems. FIG. 4 is a block diagram showing an example of the device, and FIG. 4 is a spectrum of the reproduced RF signal in FIG. 7, 9... Limiter, 8, 10... Demodulation circuit, 15
, 16...Carrier level detection circuit, 19...Amplifier, 20...Detection circuit, 22...Comparator, 23...Time constant circuit.
Claims (1)
統を複数系統備えたＦＭ信号復調器において、リ
ミツタへの入力ＦＭ信号のキヤリヤレベルが所定
レベル以下であることが所定期間継続したことを
検出するキヤリヤ検出回路を備え、キヤリヤ検出
回路の検出出力によりリミツタまたはリミツタの
出力を復調する復調回路の動作を停止せしめるこ
とを特徴とするＦＭ信号復調器。 In an FM signal demodulator equipped with multiple systems of demodulation circuits that demodulate the output of a limiter, a carrier detection circuit is provided that detects when the carrier level of the FM signal input to the limiter continues to be below a predetermined level for a predetermined period of time. 1. An FM signal demodulator comprising: a limiter or a demodulation circuit for demodulating the output of the limiter;
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16376784U JPS6179872U (en) | 1984-10-31 | 1984-10-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16376784U JPS6179872U (en) | 1984-10-31 | 1984-10-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6179872U true JPS6179872U (en) | 1986-05-28 |
Family
ID=30721629
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16376784U Pending JPS6179872U (en) | 1984-10-31 | 1984-10-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6179872U (en) |
-
1984
- 1984-10-31 JP JP16376784U patent/JPS6179872U/ja active Pending
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