JPH01153744U - - Google Patents
Info
- Publication number
- JPH01153744U JPH01153744U JP1988051153U JP5115388U JPH01153744U JP H01153744 U JPH01153744 U JP H01153744U JP 1988051153 U JP1988051153 U JP 1988051153U JP 5115388 U JP5115388 U JP 5115388U JP H01153744 U JPH01153744 U JP H01153744U
- Authority
- JP
- Japan
- Prior art keywords
- demodulator
- noise
- output
- circuit
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 230000001934 delay Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 6
Landscapes
- Circuits Of Receivers In General (AREA)
Description
第１図は本考案の一実施例の回路図、第２図は
同上のノイズ検知回路の具体回路図、第３図は同
上の動作説明図、第４図は同上の遅延回路の具体
回路図、第５図は同上の切換回路の具体回路図、
第６図は従来例の受信系の回路図である。
１は平面アンテナ、３はチユーナ、１３１，１
３２はＦＭ復調器、１４１，１４２はノイズ検知
回路、１５１，１５２は遅延回路、１６は切換回
路である。
Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a specific circuit diagram of the noise detection circuit of the above, Fig. 3 is an explanatory diagram of the operation of the same, and Fig. 4 is a specific circuit diagram of the delay circuit of the above. , Figure 5 is a specific circuit diagram of the above switching circuit,
FIG. 6 is a circuit diagram of a conventional receiving system. 1 is a planar antenna, 3 is a tuner, 13 1 , 1
3 2 is an FM demodulator, 14 1 and 14 2 are noise detection circuits, 15 1 and 15 2 are delay circuits, and 16 is a switching circuit.
Claims (1)
じて増幅及び所定の周波数に変換した後、このＦ
Ｍ変調信号を復調するＦＭ復調器を複数個備え、
ＦＭ復調器の出力に重畳されたノイズを検知する
ノイズ検知回路と、ＦＭ復調器の出力を所定時間
遅延する遅延回路とを夫々のＦＭ復調器の出力に
設け、一つのノイズ検知回路でノイズが検知され
たときその他の一つのＦＭ復調器に対応する遅延
回路の出力を選択した出力する切換回路を備え、
上記遅延回路の遅延時間をノイズ検知回路でノイ
ズが検知されて切換回路の切換が完了する時間に
設定して成ることを特徴とするチユーナ。 After amplifying the FM modulated signal received by the antenna and converting it to a predetermined frequency as necessary, this FM signal is
Equipped with a plurality of FM demodulators that demodulate the M modulation signal,
A noise detection circuit that detects the noise superimposed on the output of the FM demodulator and a delay circuit that delays the output of the FM demodulator for a predetermined time are provided at the output of each FM demodulator, so that one noise detection circuit can detect noise. comprising a switching circuit that selectively outputs the output of the delay circuit corresponding to the other one FM demodulator when detected;
A tuner characterized in that the delay time of the delay circuit is set to a time when noise is detected by the noise detection circuit and switching of the switching circuit is completed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988051153U JPH01153744U (en) | 1988-04-15 | 1988-04-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988051153U JPH01153744U (en) | 1988-04-15 | 1988-04-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01153744U true JPH01153744U (en) | 1989-10-23 |
Family
ID=31277181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988051153U Pending JPH01153744U (en) | 1988-04-15 | 1988-04-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01153744U (en) |
-
1988
- 1988-04-15 JP JP1988051153U patent/JPH01153744U/ja active Pending
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